dt-bindings: clock: convert rockchip,rk3328-cru.txt to
From: Johan Jonker <jbx6244@...> Date: Tue, 29 Mar 2022 18:30:14 +0200
Commit-Message
Convert RK3328 clock controller bindings to DT schema Changes against original bindings: - Add clocks and clock-names as the device has at least one input clock. Signed-off-by: Johan Jonker <jbx6244@...> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@...> [add Krzysztof's review from v1, shorten commit description] Signed-off-by: Heiko Stuebner <heiko@...>
Patch-Comment
.../bindings/clock/rockchip,rk3328-cru.txt | 58 --------------- .../bindings/clock/rockchip,rk3328-cru.yaml | 74 +++++++++++++++++++ 2 files changed, 74 insertions(+), 58 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.yaml
Statistics
- 74 lines added
- 58 lines removed
Changes
------- Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt --------
deleted file mode 100644
index 904ae682ea90..000000000000
@@ -1,58 +0,0 @@
------- Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.yaml -------
new file mode 100644
index 000000000000..f079c7a2559b
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/rockchip,rk3328-cru.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip RK3328 Clock and Reset Unit (CRU)
+
+maintainers:
+ - Elaine Zhang <zhangqing@rock-chips.com>
+ - Heiko Stuebner <heiko@sntech.de>
+
+description: |
+ The RK3328 clock controller generates and supplies clocks to various
+ controllers within the SoC and also implements a reset controller for SoC
+ peripherals.
+ Each clock is assigned an identifier and client nodes can use this identifier
+ to specify the clock which they consume. All available clocks are defined as
+ preprocessor macros in the dt-bindings/clock/rk3328-cru.h headers and can be
+ used in device tree sources. Similar macros exist for the reset sources in
+ these files.
+ There are several clocks that are generated outside the SoC. It is expected
+ that they are defined using standard clock bindings with following
+ clock-output-names:
+ - "xin24m" - crystal input - required,
+ - "clkin_i2s" - external I2S clock - optional,
+ - "gmac_clkin" - external GMAC clock - optional
+ - "phy_50m_out" - output clock of the pll in the mac phy
+ - "hdmi_phy" - output clock of the hdmi phy pll - optional
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rk3328-cru
+
+ reg:
+ maxItems: 1
+
+ "#clock-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: xin24m
+
+ rockchip,grf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to the syscon managing the "general register files" (GRF),
+ if missing pll rates are not changeable, due to the missing pll
+ lock status.
+
+required:
+ - compatible
+ - reg
+ - "#clock-cells"
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ cru: clock-controller@ff440000 {
+ compatible = "rockchip,rk3328-cru";
+ reg = <0xff440000 0x1000>;
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };