mmc: dw_mmc-pltfm: add Rockchip variant
From: Heiko Stuebner <heiko@...> Date: Sat, 1 Jun 2013 00:15:17 +0200
Commit-Message
Cortex-A9 SoCs from Rockchip use a slightly modified variant of dw_mmc controllers that seems to require the SDMMC_CMD_USE_HOLD_REG bit to always be set. There also seem to be no other modifications (additional register etc) present, so to keep the footprint low, add this small variant to the pltfm driver. Signed-off-by: Heiko Stuebner <heiko@...>
Patch-Comment
drivers/mmc/host/dw_mmc-pltfm.c | 21 ++++++++++++++++++++- 1 files changed, 20 insertions(+), 1 deletions(-)
Statistics
- 20 lines added
- 1 lines removed
Changes
----------------------- drivers/mmc/host/dw_mmc-pltfm.c ------------------------
index 9b05381..cbbbcf3 100644
@@ -24,6 +24,15 @@
#include "dw_mmc.h"
+static void dw_mci_rockchip_prepare_command(struct dw_mci *host, u32 *cmdr)
+{
+ *cmdr |= SDMMC_CMD_USE_HOLD_REG;
+}
+
+static const struct dw_mci_drv_data rockchip_drv_data = {
+ .prepare_command = dw_mci_rockchip_prepare_command,
+};
+
int dw_mci_pltfm_register(struct platform_device *pdev,
const struct dw_mci_drv_data *drv_data)
{
@@ -100,13 +109,23 @@ EXPORT_SYMBOL_GPL(dw_mci_pltfm_pmops);
static const struct of_device_id dw_mci_pltfm_match[] = {
{ .compatible = "snps,dw-mshc", },
+ { .compatible = "rockchip,cortex-a9-dw-mshc",
+ .data = &rockchip_drv_data },
{},
};
MODULE_DEVICE_TABLE(of, dw_mci_pltfm_match);
static int dw_mci_pltfm_probe(struct platform_device *pdev)
{
+ const struct dw_mci_drv_data *drv_data = NULL;
+ const struct of_device_id *match;
+
+ if (pdev->dev.of_node) {
+ match = of_match_node(dw_mci_pltfm_match, pdev->dev.of_node);
+ drv_data = match->data;
+ }
+
+ return dw_mci_pltfm_register(pdev, drv_data);
}
int dw_mci_pltfm_remove(struct platform_device *pdev)