ARM: dts: rockchip: add saradc nodes
From: Heiko Stuebner <heiko@...> Date: Thu, 14 Aug 2014 00:47:05 +0200
Commit-Message
Add the core device nodes for the SARADC found on both the Cortex-A9 series (rk3066 and rk3188) as well as the newer rk3288. Signed-off-by: Heiko Stuebner <heiko@...>
Patch-Comment
if nobody complains I'll queue this into my v3.18-next/dts branch arch/arm/boot/dts/rk3288.dtsi | 10 ++++++++++ arch/arm/boot/dts/rk3xxx.dtsi | 10 ++++++++++ 2 files changed, 20 insertions(+)
Statistics
- 20 lines added
- 0 lines removed
Changes
------------------------ arch/arm/boot/dts/rk3288.dtsi -------------------------
index 36be7bb..431f384 100644
@@ -98,6 +98,16 @@
status = "disabled";
};
+ saradc: saradc@ff100000 {
+ compatible = "rockchip,saradc";
+ reg = <0xff100000 0x100>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ #io-channel-cells = <1>;
+ clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
+ clock-names = "saradc", "apb_pclk";
+ status = "disabled";
+ };
+
i2c1: i2c@ff140000 {
compatible = "rockchip,rk3288-i2c";
reg = <0xff140000 0x1000>;
------------------------ arch/arm/boot/dts/rk3xxx.dtsi -------------------------
index 8caf85d..cce4a07 100644
@@ -264,4 +264,14 @@
clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
status = "disabled";
};
+
+ saradc: saradc@2006c000 {
+ compatible = "rockchip,saradc";
+ reg = <0x2006c000 0x100>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ #io-channel-cells = <1>;
+ clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
+ clock-names = "saradc", "apb_pclk";
+ status = "disabled";
+ };
};