arm64: dts: rockchip: Enable OTP controller for RK356x
From: Heiko Stuebner <heiko@...> Date: Thu, 5 Feb 2026 15:57:48 +0100
Commit-Message
Enable the One Time Programmable Controller (OTPC) in RK356x and add an initial nvmem fixed layout. Signed-off-by: Heiko Stuebner <heiko@...>
Patch-Comment
arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+)
Statistics
- 46 lines added
- 0 lines removed
Changes
---------------- arch/arm64/boot/dts/rockchip/rk356x-base.dtsi -----------------
index 8893b7b6cc9f..72c98337f359 100644
@@ -1104,6 +1104,52 @@ rng: rng@fe388000 {
status = "disabled";
};
+ otp: otp@fe38c000 {
+ compatible = "rockchip,rk3568-otp";
+ reg = <0x0 0xfe38c000 0x0 0x4000>;
+ clocks = <&cru CLK_OTPC_NS_USR>, <&cru PCLK_OTPC_NS>,
+ <&cru PCLK_OTPPHY>, <&cru CLK_OTPC_NS_SBPI>;
+ clock-names = "otp", "apb_pclk", "phy", "sbpi";
+ resets = <&cru SRST_OTPC_NS_USR>, <&cru SRST_P_OTPC_NS>,
+ <&cru SRST_OTPPHY>, <&cru SRST_OTPC_NS_SBPI>;
+ reset-names = "otp", "apb", "phy", "sbpi";
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpu_code: cpu-code@2 {
+ reg = <0x02 0x2>;
+ };
+
+ otp_cpu_version: cpu-version@8 {
+ reg = <0x08 0x1>;
+ bits = <3 3>;
+ };
+
+ otp_id: id@a {
+ reg = <0x0a 0x10>;
+ };
+
+ cpu_leakage: cpu-leakage@1a {
+ reg = <0x1a 0x1>;
+ };
+
+ log_leakage: log-leakage@1b {
+ reg = <0x1b 0x1>;
+ };
+
+ npu_leakage: npu-leakage@1c {
+ reg = <0x1c 0x1>;
+ };
+
+ gpu_leakage: gpu-leakage@1d {
+ reg = <0x1d 0x1>;
+ };
+ };
+ };
+
i2s0_8ch: i2s@fe400000 {
compatible = "rockchip,rk3568-i2s-tdm";
reg = <0x0 0xfe400000 0x0 0x1000>;