clk: rockchip: add COMPOSITE_NOGATE_DIVTBL variant
From: Heiko Stuebner <heiko@...> Date: Tue, 9 Jun 2015 14:08:44 +0200
Commit-Message
A clock branch consisting of a mux and divider with non-standard divider values. Signed-off-by: Heiko Stuebner <heiko@...>
Patch-Comment
drivers/clk/rockchip/clk.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)
Statistics
- 20 lines added
- 0 lines removed
Changes
-------------------------- drivers/clk/rockchip/clk.h --------------------------
index 92edb5f..501f02e 100644
@@ -308,6 +308,26 @@ struct rockchip_clk_branch {
.gate_offset = -1, \
}
+#define COMPOSITE_NOGATE_DIVTBL(_id, cname, pnames, f, mo, ms, \
+ mw, mf, ds, dw, df, dt) \
+ { \
+ .id = _id, \
+ .branch_type = branch_composite, \
+ .name = cname, \
+ .parent_names = pnames, \
+ .num_parents = ARRAY_SIZE(pnames), \
+ .flags = f, \
+ .muxdiv_offset = mo, \
+ .mux_shift = ms, \
+ .mux_width = mw, \
+ .mux_flags = mf, \
+ .div_shift = ds, \
+ .div_width = dw, \
+ .div_flags = df, \
+ .div_table = dt, \
+ .gate_offset = -1, \
+ }
+
#define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf)\
{ \
.id = _id, \