clk: composite: allow read-only clocks
From: Heiko Stuebner <heiko@...> Date: Mon, 19 May 2014 19:55:45 +0200
Commit-Message
This allows readl-only composite clocks by making mux_ops->set_parent and divider_ops->round_rate/set_rate optional. Signed-off-by: Heiko Stuebner <heiko@...> Acked-By: Max Schwarz <max.schwarz@...> Tested-By: Max Schwarz <max.schwarz@...>
Patch-Comment
drivers/clk/clk-composite.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-)
Statistics
- 3 lines added
- 6 lines removed
Changes
------------------------- drivers/clk/clk-composite.c --------------------------
index 9548bfc..faf7c32 100644
@@ -207,7 +207,7 @@ struct clk *clk_register_composite(struct device *dev, const char *name,
clk_composite_ops = &composite->ops;
if (mux_hw && mux_ops) {
+ if (!mux_ops->get_parent) {
clk = ERR_PTR(-EINVAL);
goto err;
}
@@ -215,7 +215,8 @@ struct clk *clk_register_composite(struct device *dev, const char *name,
composite->mux_hw = mux_hw;
composite->mux_ops = mux_ops;
clk_composite_ops->get_parent = clk_composite_get_parent;
+ if (mux_ops->set_parent)
+ clk_composite_ops->set_parent = clk_composite_set_parent;
if (mux_ops->determine_rate)
clk_composite_ops->determine_rate = clk_composite_determine_rate;
}
@@ -232,10 +233,6 @@ struct clk *clk_register_composite(struct device *dev, const char *name,
if (rate_ops->set_rate) {
clk_composite_ops->set_rate = clk_composite_set_rate;
}
}
composite->rate_hw = rate_hw;