ARM: dts: rk3188: add cru node and update device clocks to use it
From: Heiko Stuebner <heiko@...> Date: Tue, 15 Apr 2014 01:16:44 +0200
Commit-Message
This adds a node for the clock and reset unit on rk3188 SoCs and updates the device nodes retrieve their clocks from there, instead of the previous gate clock nodes. As the clocks diverge a bit until rk3066 can catch up, the shared nodes between rk3066 and rk3188 get separated clocks-properties in the rk3188.dtsi. Signed-off-by: Heiko Stuebner <heiko@...>
Patch-Comment
arch/arm/boot/dts/rk3188.dtsi | 46 +++++++++++++++++++++++++++++++++++++++---- 1 file changed, 42 insertions(+), 4 deletions(-)
Statistics
- 42 lines added
- 4 lines removed
Changes
------------------------ arch/arm/boot/dts/rk3188.dtsi -------------------------
index a494fb0..3719436 100644
@@ -15,6 +15,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/clock/rk3188-cru.h>
#include "rk3xxx.dtsi"
#include "rk3188-clocks.dtsi"
@@ -54,10 +55,12 @@
soc {
global-timer@1013c200 {
interrupts = <GIC_PPI 11 0xf04>;
+ clocks = <&cru CORE_PERI>;
};
local-timer@1013c600 {
interrupts = <GIC_PPI 13 0xf04>;
+ clocks = <&cru CORE_PERI>;
};
sram: sram@10080000 {
@@ -73,6 +76,41 @@
};
};
+ uart0: serial@10124000 {
+ clocks = <&cru SCLK_UART0>;
+ };
+
+ uart1: serial@10126000 {
+ clocks = <&cru SCLK_UART1>;
+ };
+
+ uart2: serial@20064000 {
+ clocks = <&cru SCLK_UART2>;
+ };
+
+ uart3: serial@20068000 {
+ clocks = <&cru SCLK_UART3>;
+ };
+
+ dwmmc@10214000 {
+ clocks = <&cru HCLK_MMC0>, <&cru SCLK_MMC0>;
+ clock-names = "biu", "ciu";
+ };
+
+ dwmmc@10218000 {
+ clocks = <&cru HCLK_MMC1>, <&cru SCLK_MMC1>;
+ clock-names = "biu", "ciu";
+ };
+
+ cru: cru@20000000 {
+ compatible = "rockchip,rk3188-cru";
+ reg = <0x20000000 0x1000>;
+ rockchip,grf = <&grf>;
+
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
pinctrl@20008000 {
compatible = "rockchip,rk3188-pinctrl";
rockchip,grf = <&grf>;
@@ -86,7 +124,7 @@
compatible = "rockchip,rk3188-gpio-bank0";
reg = <0x2000a000 0x100>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO0>;
gpio-controller;
#gpio-cells = <2>;
@@ -99,7 +137,7 @@
compatible = "rockchip,gpio-bank";
reg = <0x2003c000 0x100>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO1>;
gpio-controller;
#gpio-cells = <2>;
@@ -112,7 +150,7 @@
compatible = "rockchip,gpio-bank";
reg = <0x2003e000 0x100>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO2>;
gpio-controller;
#gpio-cells = <2>;
@@ -125,7 +163,7 @@
compatible = "rockchip,gpio-bank";
reg = <0x20080000 0x100>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO3>;
gpio-controller;
#gpio-cells = <2>;