RISC-V: Cache SBI vendor values

A patch from »riscv_pmu_sbi: add support for PMU variant on T-Head C9xx cores« in state Mainline for linux-kernel

From: Heiko Stuebner <heiko@...> Date: Tue, 4 Oct 2022 21:18:54 +0200

Commit-Message

sbi_get_mvendorid(), sbi_get_marchid() and sbi_get_mimpid() might get called multiple times, though the values of these CSRs should not change during the runtime of a specific machine. So cache the values in the functions and prevent multiple ecalls to read these values. As Andrew Jones noted, at least marchid and mimpid may be negative values when viewed as a long, so we use a separate static bool to indiciate the cached status. Suggested-by: Atish Patra <atishp@...> Signed-off-by: Heiko Stuebner <heiko@...>

Patch-Comment

arch/riscv/kernel/sbi.c | 30 +++++++++++++++++++++++++++--- 1 file changed, 27 insertions(+), 3 deletions(-)

Statistics

  • 27 lines added
  • 3 lines removed

Changes

--------------------------- arch/riscv/kernel/sbi.c ----------------------------
index 775d3322b422..cc618aaa9d11 100644
@@ -625,17 +625,41 @@ static inline long sbi_get_firmware_version(void)
long sbi_get_mvendorid(void)
{
- return __sbi_base_ecall(SBI_EXT_BASE_GET_MVENDORID);
+ static long id;
+ static bool cached;
+
+ if (!cached) {
+ id = __sbi_base_ecall(SBI_EXT_BASE_GET_MVENDORID);
+ cached = true;
+ }
+
+ return id;
}
long sbi_get_marchid(void)
{
- return __sbi_base_ecall(SBI_EXT_BASE_GET_MARCHID);
+ static long id;
+ static bool cached;
+
+ if (!cached) {
+ id = __sbi_base_ecall(SBI_EXT_BASE_GET_MARCHID);
+ cached = true;
+ }
+
+ return id;
}
long sbi_get_mimpid(void)
{
- return __sbi_base_ecall(SBI_EXT_BASE_GET_MIMPID);
+ static long id;
+ static bool cached;
+
+ if (!cached) {
+ id = __sbi_base_ecall(SBI_EXT_BASE_GET_MIMPID);
+ cached = true;
+ }
+
+ return id;
}
static void sbi_send_cpumask_ipi(const struct cpumask *target)
 
 

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