riscv_pmu_sbi: add support for PMU variant on T-Head C9xx cores
From: Heiko Stuebner <heiko@...> Date: Mon, 10 Oct 2022 14:15:06 +0200
The PMU on T-Head C9xx cores is quite similar to the SSCOFPMF extension but not completely identical, so this series changes in v5: - add received Reviews - fix sbi caching wrt. negative values (Drew) - add comment about specific c9xx arch- and imp-ids (Conor) changes in v4: - add new patch to cache sbi mvendor, march and mimp-ids (Atish) - errata dependencies in one line (Conor) - make driver detection conditional on CONFIG_ERRATA_THEAD_PMU too (Atish) changes in v3: - improve commit message (Atish, Conor) - IS_ENABLED and BIT() in errata probe (Conor) The change depends on my cpufeature/t-head errata probe cleanup series [1]. changes in v2: - use alternatives for the CSR access - make the irq num selection a bit nicer There is of course a matching opensbi-part whose most recent implementation can be found on [0]. [0] https://patchwork.ozlabs.org/project/opensbi/cover/20221004164227.1381825-1-heiko@sntech.de [1] https://lore.kernel.org/all/20220905111027.2463297-1-heiko@sntech.de/ Heiko Stuebner (2): RISC-V: Cache SBI vendor values drivers/perf: riscv_pmu_sbi: add support for PMU variant on T-Head C9xx cores arch/riscv/Kconfig.erratas | 13 +++++++++++ arch/riscv/errata/thead/errata.c | 19 ++++++++++++++++ arch/riscv/include/asm/errata_list.h | 16 +++++++++++++- arch/riscv/kernel/sbi.c | 30 ++++++++++++++++++++++--- drivers/perf/riscv_pmu_sbi.c | 33 +++++++++++++++++++--------- 5 files changed, 97 insertions(+), 14 deletions(-) -- 2.35.1
Patches in this set
- [0001] RISC-V: Cache SBI vendor values (raw)
- [0002] drivers/perf: riscv_pmu_sbi: add support for PMU variant (raw)
Statistics
- 2 individual patches
- 97 lines added
- 14 lines removed