ARM: S3C24XX: cleanup irq-pm integration
From: Heiko Stuebner <heiko@...> Date: Sat, 17 Nov 2012 15:24:39 +0100
Commit-Message
This patch integrates the irq-pm functions we moved in the previous patch. This includes some static attributes and the removal of the irq suspend and resume declaratons from the plat-samsung/pm.h header. Signed-off-by: Heiko Stuebner <heiko@...>
Patch-Comment
arch/arm/mach-s3c24xx/common.h | 2 ++ arch/arm/mach-s3c24xx/s3c2410.c | 4 +++- arch/arm/mach-s3c24xx/s3c2412.c | 4 +++- arch/arm/mach-s3c24xx/s3c2416.c | 4 +++- arch/arm/mach-s3c24xx/s3c2440.c | 4 +++- arch/arm/mach-s3c24xx/s3c2442.c | 4 +++- arch/arm/plat-s3c24xx/irq.c | 22 +++++++++++----------- arch/arm/plat-samsung/include/plat/pm.h | 6 ------ 8 files changed, 28 insertions(+), 22 deletions(-)
Statistics
- 28 lines added
- 22 lines removed
Changes
------------------------ arch/arm/mach-s3c24xx/common.h ------------------------
index c2f596e..ed6276f 100644
@@ -15,4 +15,6 @@
void s3c2410_restart(char mode, const char *cmd);
void s3c244x_restart(char mode, const char *cmd);
+extern struct syscore_ops s3c24xx_irq_syscore_ops;
+
#endif /* __ARCH_ARM_MACH_S3C24XX_COMMON_H */
----------------------- arch/arm/mach-s3c24xx/s3c2410.c ------------------------
index a3c5cb0..9ebef95 100644
@@ -49,6 +49,8 @@
#include <plat/gpio-cfg.h>
#include <plat/gpio-cfg-helpers.h>
+#include "common.h"
+
/* Initial IO mappings */
static struct map_desc s3c2410_iodesc[] __initdata = {
@@ -182,8 +184,8 @@ int __init s3c2410_init(void)
#ifdef CONFIG_PM
register_syscore_ops(&s3c2410_pm_syscore_ops);
register_syscore_ops(&s3c24xx_irq_syscore_ops);
+#endif
return device_register(&s3c2410_dev);
}
----------------------- arch/arm/mach-s3c24xx/s3c2412.c ------------------------
index 6c5f403..0ec08bd 100644
@@ -51,6 +51,8 @@
#include <plat/pll.h>
#include <plat/nand-core.h>
+#include "common.h"
+
#ifndef CONFIG_CPU_S3C2412_ONLY
void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO;
@@ -244,8 +246,8 @@ int __init s3c2412_init(void)
#ifdef CONFIG_PM
register_syscore_ops(&s3c2412_pm_syscore_ops);
register_syscore_ops(&s3c24xx_irq_syscore_ops);
+#endif
return device_register(&s3c2412_dev);
}
----------------------- arch/arm/mach-s3c24xx/s3c2416.c ------------------------
index 77ee0b7..e30476d 100644
@@ -63,6 +63,8 @@
#include <plat/rtc-core.h>
#include <plat/spi-core.h>
+#include "common.h"
+
static struct map_desc s3c2416_iodesc[] __initdata = {
IODESC_ENT(WATCHDOG),
IODESC_ENT(CLKPWR),
@@ -105,9 +107,9 @@ int __init s3c2416_init(void)
#ifdef CONFIG_PM
register_syscore_ops(&s3c2416_pm_syscore_ops);
register_syscore_ops(&s3c24xx_irq_syscore_ops);
register_syscore_ops(&s3c2416_irq_syscore_ops);
+#endif
return device_register(&s3c2416_dev);
}
----------------------- arch/arm/mach-s3c24xx/s3c2440.c ------------------------
index 2b3dddb..559e394 100644
@@ -40,6 +40,8 @@
#include <plat/gpio-cfg.h>
#include <plat/gpio-cfg-helpers.h>
+#include "common.h"
+
static struct device s3c2440_dev = {
.bus = &s3c2440_subsys,
};
@@ -57,9 +59,9 @@ int __init s3c2440_init(void)
#ifdef CONFIG_PM
register_syscore_ops(&s3c2410_pm_syscore_ops);
+ register_syscore_ops(&s3c24xx_irq_syscore_ops);
#endif
register_syscore_ops(&s3c244x_pm_syscore_ops);
/* register our system device for everything else */
----------------------- arch/arm/mach-s3c24xx/s3c2442.c ------------------------
index 22cb7c9..f732826 100644
@@ -51,6 +51,8 @@
#include <plat/gpio-cfg.h>
#include <plat/gpio-cfg-helpers.h>
+#include "common.h"
+
/* S3C2442 extended clock support */
static unsigned long s3c2442_camif_upll_round(struct clk *clk,
@@ -172,9 +174,9 @@ int __init s3c2442_init(void)
#ifdef CONFIG_PM
register_syscore_ops(&s3c2410_pm_syscore_ops);
+ register_syscore_ops(&s3c24xx_irq_syscore_ops);
#endif
register_syscore_ops(&s3c244x_pm_syscore_ops);
return device_register(&s3c2442_dev);
}
------------------------- arch/arm/plat-s3c24xx/irq.c --------------------------
index 7ce4f84..bac8053 100644
@@ -119,25 +119,25 @@ static inline void s3c_irq_maskack(struct irq_data *data)
}
#ifdef CONFIG_PM
+/* state for IRQs over sleep
*
+ * default is to allow for EINT0..EINT15, and IRQ_RTC as wakeup sources
* set bit to 1 in allow bitfield to enable the wakeup settings on it
+ */
+unsigned long s3c_irqwake_intallow = 1L << 30 | 0xfL;
unsigned long s3c_irqwake_eintallow = 0x0000fff0L;
+/* FIXME: must not be static until s3c2412 irqs are included */
int s3c_irq_wake(struct irq_data *data, unsigned int state)
{
+ unsigned long irqbit = 1 << data->hwirq;
if (!(s3c_irqwake_intallow & irqbit))
return -ENOENT;
+ pr_info("wake %s for hwirq %lu\n",
+ state ? "enabled" : "disabled", data->hwirq);
if (!state)
s3c_irqwake_intmask |= irqbit;
@@ -726,7 +726,7 @@ static unsigned long save_extint[3];
static unsigned long save_eintflt[4];
static unsigned long save_eintmask;
+static int s3c24xx_irq_suspend(void)
{
unsigned int i;
@@ -742,7 +742,7 @@ int s3c24xx_irq_suspend(void)
return 0;
}
+static void s3c24xx_irq_resume(void)
{
unsigned int i;
@@ -755,9 +755,9 @@ void s3c24xx_irq_resume(void)
s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
__raw_writel(save_eintmask, S3C24XX_EINTMASK);
}
struct syscore_ops s3c24xx_irq_syscore_ops = {
.suspend = s3c24xx_irq_suspend,
.resume = s3c24xx_irq_resume,
};
+#endif
------------------- arch/arm/plat-samsung/include/plat/pm.h --------------------
index 61fc537..b86dcca 100644
@@ -108,16 +108,10 @@ extern void s3c_pm_do_restore_core(struct sleep_save *ptr, int count);
#ifdef CONFIG_PM
extern int s3c_irqext_wake(struct irq_data *data, unsigned int state);
#else
#define s3c_irqext_wake NULL
#endif
/* PM debug functions */
#ifdef CONFIG_SAMSUNG_PM_DEBUG