clk: rockchip: Allow the RK3288 SPDIF clocks to change their parent
From: Sjoerd Simons <sjoerd.simons@...> Date: Thu, 8 Oct 2015 15:31:16 +0200
Commit-Message
The clock branches leading to sclk_spdif and sclk_spdif_8ch on RK3288 SoCs only feed those clocks, allow those clocks to change their parents all the way up the hierarchy. Signed-off-by: Sjoerd Simons <sjoerd.simons@...> Signed-off-by: Heiko Stuebner <heiko@...>
Patch-Comment
drivers/clk/rockchip/clk-rk3288.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-)
Statistics
- 8 lines added
- 8 lines removed
Changes
---------------------- drivers/clk/rockchip/clk-rk3288.c -----------------------
index e0bb0f0..80065e6 100644
@@ -317,25 +317,25 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
MUX(0, "spdif_src", mux_pll_src_cpll_gpll_p, 0,
RK3288_CLKSEL_CON(5), 15, 1, MFLAGS),
+ COMPOSITE_NOMUX(0, "spdif_pre", "spdif_src", CLK_SET_RATE_PARENT,
RK3288_CLKSEL_CON(5), 0, 7, DFLAGS,
RK3288_CLKGATE_CON(4), 4, GFLAGS),
+ COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_src", CLK_SET_RATE_PARENT,
RK3288_CLKSEL_CON(9), 0,
RK3288_CLKGATE_CON(4), 5, GFLAGS,
+ MUX(0, "spdif_mux", mux_spdif_p, CLK_SET_RATE_PARENT,
RK3288_CLKSEL_CON(5), 8, 2, MFLAGS)),
+ GATE(SCLK_SPDIF, "sclk_spdif", "spdif_mux", CLK_SET_RATE_PARENT,
RK3288_CLKGATE_CON(4), 6, GFLAGS),
+ COMPOSITE_NOMUX(0, "spdif_8ch_pre", "spdif_src", CLK_SET_RATE_PARENT,
RK3288_CLKSEL_CON(40), 0, 7, DFLAGS,
RK3288_CLKGATE_CON(4), 7, GFLAGS),
+ COMPOSITE_FRACMUX(0, "spdif_8ch_frac", "spdif_8ch_pre", CLK_SET_RATE_PARENT,
RK3288_CLKSEL_CON(41), 0,
RK3288_CLKGATE_CON(4), 8, GFLAGS,
+ MUX(0, "spdif_8ch_mux", mux_spdif_8ch_p, CLK_SET_RATE_PARENT,
RK3288_CLKSEL_CON(40), 8, 2, MFLAGS)),
+ GATE(SCLK_SPDIF8CH, "sclk_spdif_8ch", "spdif_8ch_mux", CLK_SET_RATE_PARENT,
RK3288_CLKGATE_CON(4), 9, GFLAGS),
GATE(0, "sclk_acc_efuse", "xin24m", 0,