drm/rockchip: vop2: fix rk3588 dp+dsi maxclk verification

A patch from »drm/rockchip: vop2: fix rk3588 dp+dsi maxclk verification« in state Mainline for linux-kernel

From: Heiko Stuebner <heiko.stuebner@...> Date: Sun, 24 Dec 2023 19:31:28 +0100

Commit-Message

The clock is in Hz while the value checked against is in kHz, so actual frequencies will never be able to be below to max value. Fix this by specifying the max-value in Hz too. Fixes: 5a028e8f062f ("drm/rockchip: vop2: Add support for rk3588") Signed-off-by: Heiko Stuebner <heiko.stuebner@...> Reviewed-by: Quentin Schulz <quentin.schulz@...> Acked-by: Andy Yan<andyshrk@...>

Patch-Comment

changes in v2: - drop the separate vp3-config patch, as vp3 will always get the leftover resources, so _should_ be fine (Andy) - fix error output to also report Hz for the value in Hz (Quentin) - add received Reviews+Acks drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)

Statistics

  • 4 lines added
  • 4 lines removed

Changes

----------------- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c -----------------
index 9ad025aa9ab0..0c8ec7220fbe 100644
@@ -1864,9 +1864,9 @@ static unsigned long rk3588_calc_cru_cfg(struct vop2_video_port *vp, int id,
else
dclk_out_rate = v_pixclk >> 2;
- dclk_rate = rk3588_calc_dclk(dclk_out_rate, 600000);
+ dclk_rate = rk3588_calc_dclk(dclk_out_rate, 600000000);
if (!dclk_rate) {
- drm_err(vop2->drm, "DP dclk_out_rate out of range, dclk_out_rate: %ld KHZ\n",
+ drm_err(vop2->drm, "DP dclk_out_rate out of range, dclk_out_rate: %ld Hz\n",
dclk_out_rate);
return 0;
}
@@ -1881,9 +1881,9 @@ static unsigned long rk3588_calc_cru_cfg(struct vop2_video_port *vp, int id,
* dclk_rate = N * dclk_core_rate N = (1,2,4 ),
* we get a little factor here
*/
- dclk_rate = rk3588_calc_dclk(dclk_out_rate, 600000);
+ dclk_rate = rk3588_calc_dclk(dclk_out_rate, 600000000);
if (!dclk_rate) {
- drm_err(vop2->drm, "MIPI dclk out of range, dclk_out_rate: %ld KHZ\n",
+ drm_err(vop2->drm, "MIPI dclk out of range, dclk_out_rate: %ld Hz\n",
dclk_out_rate);
return 0;
}
 
 

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