drm/rockchip: vop2: configure layers for vp3 on rk3588
From: Heiko Stuebner <heiko.stuebner@...> Date: Wed, 10 Apr 2024 06:28:16 +0200
Commit-Message
The rk3588 VOP2 has 4 video-ports, yet the driver currently only configures the first 3, as used on the rk3568. Add another block to configure the vp3 as well, if applicable. Fixes: 5a028e8f062f ("drm/rockchip: vop2: Add support for rk3588") Signed-off-by: Heiko Stuebner <heiko.stuebner@...>
Patch-Comment
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 12 ++++++++++++ drivers/gpu/drm/rockchip/rockchip_drm_vop2.h | 1 + 2 files changed, 13 insertions(+)
Statistics
- 13 lines added
- 0 lines removed
Changes
----------------- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c -----------------
index 523880a4e8e74..1a327a9ed7ee4 100644
@@ -2303,6 +2303,7 @@ static void vop2_setup_alpha(struct vop2_video_port *vp)
static void vop2_setup_layer_mixer(struct vop2_video_port *vp)
{
struct vop2 *vop2 = vp->vop2;
+ const struct vop2_data *vop2_data = vop2->data;
struct drm_plane *plane;
u32 layer_sel = 0;
u32 port_sel;
@@ -2344,6 +2345,17 @@ static void vop2_setup_layer_mixer(struct vop2_video_port *vp)
else
port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT2_MUX, 8);
+ /* configure vp3 */
+ if (vop2_data->soc_id == 3588) {
+ struct vop2_video_port *vp3 = &vop2->vps[3];
+
+ if (vp3->nlayers)
+ port_sel |= FIELD_PREP(RK3588_OVL_PORT_SET__PORT3_MUX,
+ (vp3->nlayers + vp2->nlayers + vp1->nlayers + vp0->nlayers - 1));
+ else
+ port_sel |= FIELD_PREP(RK3588_OVL_PORT_SET__PORT3_MUX, 8);
+ }
+
layer_sel = vop2_readl(vop2, RK3568_OVL_LAYER_SEL);
ofs = 0;
----------------- drivers/gpu/drm/rockchip/rockchip_drm_vop2.h -----------------
index 615a16196aff6..f46fb795414e1 100644
@@ -489,6 +489,7 @@ enum dst_factor_mode {
#define RK3588_OVL_PORT_SEL__CLUSTER2 GENMASK(21, 20)
#define RK3568_OVL_PORT_SEL__CLUSTER1 GENMASK(19, 18)
#define RK3568_OVL_PORT_SEL__CLUSTER0 GENMASK(17, 16)
+#define RK3588_OVL_PORT_SET__PORT3_MUX GENMASK(15, 12)
#define RK3568_OVL_PORT_SET__PORT2_MUX GENMASK(11, 8)
#define RK3568_OVL_PORT_SET__PORT1_MUX GENMASK(7, 4)
#define RK3568_OVL_PORT_SET__PORT0_MUX GENMASK(3, 0)