clk: rockchip: rk3588: make refclko25m_ethX critical
From: Heiko Stuebner <heiko.stuebner@...> Date: Sat, 14 Dec 2024 22:56:22 +0100
Commit-Message
Ethernet phys normally need a 25MHz refclk input. On a lot of boards this is done with a dedicated 25MHz crystal. But the rk3588 CRU also provides a means for that via the refclko25m_ethX clock outputs that can be used for that function. The mdio bus normally probes devices on the bus at runtime, by reading specific phy registers. This requires the phy to be running and thus also being supplied by its reference clock. While there exist the possibility and dt-binding to declare these input clocks for each phy in the phy-dt-node, this is only relevant _after_ the phy has been detected and during the drivers probe-run. This results in a chicken-and-egg-problem. The refclks in the CRU are running on boot of course, but phy-probing can very well happen after clk_disable_unused has run. In the past I tried to make clock-handling part of the mdio bus code [0] but that wasn't very well received, due to it being specific to OF and clocks with the consensus being that resources needed for detection need to be enabled before. So to make probing ethernet phys using the internal refclks possible, make those 2 clocks critical. [0] https://lore.kernel.org/netdev/13590315.F0gNSz5aLb@diego/T/ Signed-off-by: Heiko Stuebner <heiko.stuebner@...>
Patch-Comment
drivers/clk/rockchip/clk-rk3588.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
Statistics
- 2 lines added
- 2 lines removed