dt-bindings: reset: fix double id on rk3562-cru reset ids

A patch from »dt-bindings: reset: fix double id on rk3562-cru reset ids« in state Mainline for linux-kernel

From: Heiko Stuebner <heiko@...> Date: Wed, 12 Mar 2025 22:49:39 +0100

Commit-Message

Id 173 was accidentially used two times for SRST_P_DDR_HWLP and SRST_P_DDR_PHY. This makes both resets ambiguous and also causes build warnings like: drivers/clk/rockchip/rst-rk3562.c:21:57: error: initialized field overwritten [-Werror=override-init] 21 | #define RK3562_DDRCRU_RESET_OFFSET(id, reg, bit) [id] = (0x20000*4 + reg * 16 + bit) | ^ drivers/clk/rockchip/rst-rk3562.c:266:9: note: in expansion of macro 'RK3562_DDRCRU_RESET_OFFSET' 266 | RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_PHY, 0, 8), | ^~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/clk/rockchip/rst-rk3562.c:21:57: note: (near initialization for 'rk3562_register_offset[173]') 21 | #define RK3562_DDRCRU_RESET_OFFSET(id, reg, bit) [id] = (0x20000*4 + reg * 16 + bit) | ^ drivers/clk/rockchip/rst-rk3562.c:266:9: note: in expansion of macro 'RK3562_DDRCRU_RESET_OFFSET' 266 | RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_PHY, 0, 8), | ^~~~~~~~~~~~~~~~~~~~~~~~~~ To fix that issue give SRST_P_DDR_PHY a new and now unique id. Reported-by: Stephen Boyd <sboyd@...> Reported-by: kernel test robot <lkp@...> Closes: https://lore.kernel.org/oe-kbuild-all/202503121743.0zcDf6nE-lkp@intel.com/ Fixes: dd113c4fefc8 ("dt-bindings: clock: Add RK3562 cru") Signed-off-by: Heiko Stuebner <heiko@...>

Patch-Comment

The original patch did go with the reset of the clock controller code into the clock tree, so this patch should of course also go that way. I also don't have anything more open for the 6.15 merge window, so clock-maintainers could just apply this patch on top of the main changes. include/dt-bindings/reset/rockchip,rk3562-cru.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

Statistics

  • 1 lines added
  • 1 lines removed

Changes

--------------- include/dt-bindings/reset/rockchip,rk3562-cru.h ----------------
index a74471d7d2a93..8df95113056e3 100644
@@ -217,7 +217,7 @@
#define SRST_MSCH_BRG_BIU 171
#define SRST_P_MSCH_BIU 172
#define SRST_P_DDR_HWLP 173
-#define SRST_P_DDR_PHY 173
+#define SRST_P_DDR_PHY 290
#define SRST_P_DDR_DFICTL 174
#define SRST_P_DDR_DMA2DDR 175
/********Name=DDRSOFTRST_CON01,Offset=0x20204********/
 
 

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