arm64: dts: rockchip: convert rk3562 to their dt-binding
From: Heiko Stuebner <heiko@...> Date: Sat, 10 May 2025 15:37:07 +0200
Commit-Message
Now that the binding head has been merged, convert the power-domain ids back to these constants for easier handling. Signed-off-by: Heiko Stuebner <heiko@...>
Patch-Comment
arch/arm64/boot/dts/rockchip/rk3562.dtsi | 37 ++++++++++++------------ 1 file changed, 19 insertions(+), 18 deletions(-)
Statistics
- 19 lines added
- 18 lines removed
Changes
------------------- arch/arm64/boot/dts/rockchip/rk3562.dtsi -------------------
index 0156f969c4bc..412ecad79b0d 100644
@@ -7,6 +7,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/power/rockchip,rk3562-power.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/reset/rockchip,rk3562-cru.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>
@@ -546,48 +547,48 @@ power: power-controller {
#size-cells = <0>;
status = "okay";
+ power-domain@RK3562_PD_GPU {
+ reg = <RK3562_PD_GPU>;
pm_qos = <&qos_gpu>;
#power-domain-cells = <0>;
};
+ power-domain@RK3562_PD_NPU {
+ reg = <RK3562_PD_NPU>;
pm_qos = <&qos_npu>;
#power-domain-cells = <0>;
};
+ power-domain@RK3562_PD_VDPU {
+ reg = <RK3562_PD_VDPU>;
pm_qos = <&qos_rkvdec>;
#power-domain-cells = <0>;
};
+ power-domain@RK3562_PD_VI {
+ reg = <RK3562_PD_VI>;
#power-domain-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
pm_qos = <&qos_isp>,
<&qos_vicap>;
+ power-domain@RK3562_PD_VEPU {
+ reg = <RK3562_PD_VEPU>;
pm_qos = <&qos_vepu>;
#power-domain-cells = <0>;
};
};
+ power-domain@RK3562_PD_VO {
+ reg = <RK3562_PD_VO>;
#power-domain-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
pm_qos = <&qos_vop>;
+ power-domain@RK3562_PD_RGA {
+ reg = <RK3562_PD_RGA>;
pm_qos = <&qos_rga_rd>,
<&qos_rga_wr>,
<&qos_jpeg>;
@@ -595,8 +596,8 @@ power-domain@14 {
};
};
+ power-domain@RK3562_PD_PHP {
+ reg = <RK3562_PD_PHP>;
pm_qos = <&qos_pcie>,
<&qos_usb3>;
#power-domain-cells = <0>;
@@ -616,7 +617,7 @@ gpu: gpu@ff320000 {
<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "job", "mmu", "gpu";
operating-points-v2 = <&gpu_opp_table>;
+ power-domains = <&power RK3562_PD_GPU>;
#cooling-cells = <2>;
status = "disabled";
};
@@ -653,7 +654,7 @@ pcie2x1: pcie@ff500000 {
num-lanes = <1>;
phys = <&combphy_pu PHY_TYPE_PCIE>;
phy-names = "pcie-phy";
+ power-domains = <&power RK3562_PD_PHP>;
ranges = <0x01000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x100000
0x02000000 0x0 0xfc200000 0x0 0xfc200000 0x0 0x1e00000
0x03000000 0x3 0x00000000 0x3 0x00000000 0x0 0x40000000>;