clk: rockchip: fix DPHY gate locations on rk3368

A patch from »clk: rockchip: add clock ids for PCLK_DPHYRX and« in state Mainline for linux-kernel

From: Heiko Stuebner <heiko.stuebner@...> Date: Thu, 4 Feb 2021 15:30:03 +0100

Commit-Message

Fix the register and bits of the DPHY gate locations. Signed-off-by: Heiko Stuebner <heiko.stuebner@...>

Patch-Comment

drivers/clk/rockchip/clk-rk3368.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

Statistics

  • 2 lines added
  • 2 lines removed

Changes

---------------------- drivers/clk/rockchip/clk-rk3368.c -----------------------
index 61413be48d1a..9a0dab9448db 100644
@@ -818,8 +818,8 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
* pclk_vio gates
* pclk_vio comes from the exactly same source as hclk_vio
*/
- GATE(PCLK_DPHYRX, "pclk_dphyrx", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(14), 8, GFLAGS),
- GATE(PCLK_DPHYTX0, "pclk_dphytx0", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(14), 8, GFLAGS),
+ GATE(PCLK_DPHYRX, "pclk_dphyrx", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(22), 11, GFLAGS),
+ GATE(PCLK_DPHYTX0, "pclk_dphytx0", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(22), 10, GFLAGS),
/* pclk_pd_pmu gates */
GATE(PCLK_PMUGRF, "pclk_pmugrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 5, GFLAGS),
 
 

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