PatchTrack

From: Heiko Stuebner <heiko@...> Date: Mon, 29 Nov 2021 09:40:07 +0800

Commit-Message

This patch follows the standard pure RISC-V Svpbmt extension in privilege spec to solve the non-coherent SOC dma synchronization issues. Here is the svpbmt PTE format: | 63 | 62-61 | 60-8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 N MT RSW D A G U X W R V ^ Of the Reserved bits [63:54] in a leaf PTE, the high bit is already allocated (as the N bit), so bits [62:61] are used as the MT (aka MemType) field. This field specifies one of three memory types that are close equivalents (or equivalent in effect) to the three main x86 and ARMv8 memory types - as shown in the following table. RISC-V Encoding & MemType RISC-V Description ---------- ------------------------------------------------ 00 - PMA Normal Cacheable, No change to implied PMA memory type 01 - NC Non-cacheable, idempotent, weakly-ordered Main Memory 10 - IO Non-cacheable, non-idempotent, strongly-ordered I/O memory 11 - Rsvd Reserved for future standard use The standard protection_map[] needn't be modified because the "PMA" type keeps the highest bits zero. And the whole modification is limited in the arch/riscv/* and using a global variable (__svpbmt) as _PAGE_MASK/IO/NOCACHE for pgprot_noncached (&writecombine) in pgtable.h. We also add _PAGE_CHG_MASK to filter PFN than before. Enable it in devicetree - (Add "riscv,svpbmt" in the mmu of cpu node) - mmu: riscv,svpmbt Signed-off-by: Heiko Stuebner <heiko@...>

Patch-Comment

arch/riscv/errata/cpufeatures.c | 32 +++++++++++++++ arch/riscv/include/asm/errata_list.h | 12 +++++- arch/riscv/include/asm/fixmap.h | 2 - arch/riscv/include/asm/pgtable-32.h | 10 +++++ arch/riscv/include/asm/pgtable-64.h | 59 +++++++++++++++++++++++++++ arch/riscv/include/asm/pgtable-bits.h | 4 -- arch/riscv/include/asm/pgtable.h | 32 ++++++++++++--- 7 files changed, 138 insertions(+), 13 deletions(-)

Statistics

• 138 lines added
• 13 lines removed

Changes