RISC-V: add rd reg parsing to parse_asm header
From: Heiko Stuebner <heiko.stuebner@...> Date: Thu, 3 Nov 2022 11:45:47 +0100
Commit-Message
Add a macro to allow parsing of the rd register from an instruction. Signed-off-by: Heiko Stuebner <heiko.stuebner@...>
Patch-Comment
arch/riscv/include/asm/insn.h | 5 +++++ 1 file changed, 5 insertions(+)
Statistics
- 5 lines added
- 0 lines removed
Changes
------------------------ arch/riscv/include/asm/insn.h -------------------------
index 1caed8fe5204..ef4b1c18cbdc 100644
@@ -60,6 +60,7 @@
#define RVG_RS1_OPOFF 15
#define RVG_RS2_OPOFF 20
#define RVG_RD_OPOFF 7
+#define RVG_RD_MASK GENMASK(4, 0)
/* The bit field of immediate value in RVC J instruction */
#define RVC_J_IMM_SIGN_OPOFF 12
@@ -244,6 +245,10 @@ static __always_inline bool riscv_insn_is_branch(u32 code)
#define RV_X(X, s, mask) (((X) >> (s)) & (mask))
#define RVC_X(X, s, mask) RV_X(X, s, mask)
+#define RV_EXTRACT_RD_REG(x) \
+ ({typeof(x) x_ = (x); \
+ (RV_X(x_, RVG_RD_OPOFF, RVG_RD_MASK)); })
+
#define RV_EXTRACT_UTYPE_IMM(x) \
({typeof(x) x_ = (x); \
(RV_X(x_, RV_U_IMM_31_12_OPOFF, RV_U_IMM_31_12_MASK)); })