PatchTrack

From: Heiko Stuebner <heiko@...> Date: Fri, 10 Jun 2022 02:38:44 +0200

This series is based on the alternatives changes done in my svpbmt series and thus also depends on Atish's isa-extension parsing series. It implements using the cache-management instructions from the Zicbom- extension to handle cache flush, etc actions on platforms needing them. SoCs using cpu cores from T-Head like the Allwinne D1 implement a different set of cache instructions. But while they are different, instructions they provide the same functionality, so a variant can easly hook into the existing alternatives mechanism on those. An ongoing discussion is about the currently used pre-coded instructions. Palmer's current thinking is that we should wait until the relevant instructions have landed in binutils. On the other hand this would result in massive waiting times for all new instructions in the future as well, as it isn't only the time till a binutils patch is accepted but also then the wait for the next release and _after_ that the wait until these new releases are available in regular distributions. So ideally it would be nice to find some sort of compromise in the middle somewhere. The series sits on top of my svpbmt fixup series, which for example includes the conversion away from function pointers for the check-functions. And also uses my nops-series. changes in v3: - rebase onto 5.19-rc1 + svpbmt-fixup-series - adapt wording for block-size binding - include asm/cacheflush.h into dma-noncoherent to fix the no-prototype error clang seems to generate - use __nops macro for readability - add some received tags - add a0 to the clobber list changes in v2: - cbom-block-size is hardware-specific and comes from firmware - update Kconfig name to use the ISA extension name - select the ALTERNATIVES symbol when enabled - shorten the line lengths of the errata-assembly Heiko Stuebner (3): dt-bindings: riscv: document cbom-block-size riscv: Implement Zicbom-based cache management operations riscv: implement cache-management errata for T-Head SoCs .../devicetree/bindings/riscv/cpus.yaml | 5 + arch/riscv/Kconfig | 15 +++ arch/riscv/Kconfig.erratas | 10 ++ arch/riscv/errata/thead/errata.c | 15 +++ arch/riscv/include/asm/cacheflush.h | 6 ++ arch/riscv/include/asm/errata_list.h | 76 ++++++++++++++- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpu.c | 1 + arch/riscv/kernel/cpufeature.c | 18 ++++ arch/riscv/kernel/setup.c | 2 + arch/riscv/mm/Makefile | 1 + arch/riscv/mm/dma-noncoherent.c | 93 +++++++++++++++++++ 12 files changed, 241 insertions(+), 2 deletions(-) create mode 100644 arch/riscv/mm/dma-noncoherent.c -- 2.35.1

Patches in this set

• [0001] dt-bindings: riscv: document cbom-block-size (raw)
• [0002] riscv: Implement Zicbom-based cache management operations (raw)
• [0003] riscv: implement cache-management errata for T-Head SoCs (raw)

Statistics

• 3 individual patches
• 245 lines added
• 6 lines removed