arm64: dts: rockchip: add px30 otp controller
From: Heiko Stuebner <heiko@...> Date: Mon, 23 Sep 2019 12:41:55 +0200
Commit-Message
The px30 soc contains a controller for one-time-programmable memory, so add the necessary node for it and the fields defined in it by default. Signed-off-by: Heiko Stuebner <heiko@...>
Patch-Comment
arch/arm64/boot/dts/rockchip/px30.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)
Statistics
- 24 lines added
- 0 lines removed
Changes
-------------------- arch/arm64/boot/dts/rockchip/px30.dtsi --------------------
index dd58b1bc5981..767f3ce6e9f7 100644
@@ -664,6 +664,30 @@
status = "disabled";
};
+ otp: nvmem@ff290000 {
+ compatible = "rockchip,px30-otp";
+ reg = <0x0 0xff290000 0x0 0x4000>;
+ clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
+ <&cru PCLK_OTP_PHY>;
+ clock-names = "otp", "apb_pclk", "phy";
+ resets = <&cru SRST_OTP_PHY>;
+ reset-names = "phy";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* Data cells */
+ cpu_id: id@7 {
+ reg = <0x07 0x10>;
+ };
+ cpu_leakage: cpu-leakage@17 {
+ reg = <0x17 0x1>;
+ };
+ performance: performance@1e {
+ reg = <0x1e 0x1>;
+ bits = <4 3>;
+ };
+ };
+
cru: clock-controller@ff2b0000 {
compatible = "rockchip,px30-cru";
reg = <0x0 0xff2b0000 0x0 0x1000>;