clk: fractional-divider: cast parent_rate to u64 before multiplying
From: Heiko Stuebner <heiko@...> Date: Thu, 28 Aug 2014 12:33:07 +0200
Commit-Message
On 32bit architectures, like ARM calculating the fractional rate will do the multiplication before converting the value to u64 when it gets assigned to ret, which can produce overflows. The error in question happened with a parent_rate of 386MHz, m = 3000, n = 60000, which resulted in a wrong rate value of 15812Hz. Therefore cast parent_rate to u64 to make sure the multiplication happens in a 64bit space and produces the correct 192MHz in the example. Signed-off-by: Heiko Stuebner <heiko@...>
Patch-Comment
drivers/clk/clk-fractional-divider.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Statistics
- 1 lines added
- 1 lines removed
Changes
--------------------- drivers/clk/clk-fractional-divider.c ---------------------
index ede685c..82a59d0 100644
@@ -36,7 +36,7 @@ static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,
m = (val & fd->mmask) >> fd->mshift;
n = (val & fd->nmask) >> fd->nshift;
+ ret = (u64)parent_rate * m;
do_div(ret, n);
return ret;