ARM: S3C24XX: add handle_irq function
From: Heiko Stuebner <heiko@...> Date: Thu, 21 Feb 2013 01:01:44 +0100
Commit-Message
This removes the dependency on static irq mappings for basic irq handling and makes the s3c24xx entry-macro.S obsolete. Also the interrupts of the second full interrupt controller on the s3c2416 are really handled now, which was forgotten when adding them. The handling itself does the same as the previous assembler-code in that it tries to get the interrupt offset from the offset register first and if that produces wrong results manually searches for the interrupt bit in the pending register value. It also saves the historic comment which explains the reason behind this. Signed-off-by: Heiko Stuebner <heiko@...>
Patch-Comment
arch/arm/Kconfig | 1 + arch/arm/mach-s3c24xx/include/mach/entry-macro.S | 70 ---------------------- arch/arm/mach-s3c24xx/irq.c | 58 ++++++++++++++++++ 3 files changed, 59 insertions(+), 70 deletions(-) delete mode 100644 arch/arm/mach-s3c24xx/include/mach/entry-macro.S
Statistics
- 59 lines added
- 70 lines removed
Changes
------------------------------- arch/arm/Kconfig -------------------------------
index aacea44..23e894e 100644
@@ -777,6 +777,7 @@ config ARCH_S3C24XX
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C2410_WATCHDOG if WATCHDOG
select HAVE_S3C_RTC if RTC_CLASS
+ select MULTI_IRQ_HANDLER
select NEED_MACH_GPIO_H
select NEED_MACH_IO_H
help
--------------- arch/arm/mach-s3c24xx/include/mach/entry-macro.S ---------------
deleted file mode 100644
index 6a21bee..0000000
@@ -1,70 +0,0 @@
------------------------- arch/arm/mach-s3c24xx/irq.c --------------------------
index 8bc2931..5c9f8b7 100644
@@ -26,6 +26,7 @@
#include <linux/device.h>
#include <linux/irqdomain.h>
+#include <asm/exception.h>
#include <asm/mach/irq.h>
#include <mach/regs-irq.h>
@@ -282,6 +283,56 @@ static void s3c_irq_demux(unsigned int irq, struct irq_desc *desc)
chained_irq_exit(chip, desc);
}
+static struct s3c_irq_intc *main_intc;
+static struct s3c_irq_intc *main_intc2;
+
+static inline int s3c24xx_handle_intc(struct s3c_irq_intc *intc,
+ struct pt_regs *regs)
+{
+ int pnd;
+ int offset;
+ int irq;
+
+ pnd = __raw_readl(intc->reg_intpnd);
+ if (!pnd)
+ return false;
+
+ /* We have a problem that the INTOFFSET register does not always
+ * show one interrupt. Occasionally we get two interrupts through
+ * the prioritiser, and this causes the INTOFFSET register to show
+ * what looks like the logical-or of the two interrupt numbers.
+ *
+ * Thanks to Klaus, Shannon, et al for helping to debug this problem
+ */
+ offset = __raw_readl(intc->reg_intpnd + 4);
+
+ /* Find the bit manually, when the offset is wrong.
+ * The pending register only ever contains the one bit of the next
+ * interrupt to handle.
+ */
+ if (!(pnd & (1 << offset)))
+ offset = __ffs(pnd);
+
+ irq = irq_find_mapping(intc->domain, offset);
+ handle_IRQ(irq, regs);
+ return true;
+}
+
+asmlinkage void __exception_irq_entry s3c24xx_handle_irq(struct pt_regs *regs)
+{
+ do {
+ if (likely(main_intc))
+ if (s3c24xx_handle_intc(main_intc, regs))
+ continue;
+
+ if (main_intc2)
+ if (s3c24xx_handle_intc(main_intc2, regs))
+ continue;
+
+ break;
+ } while (1);
+}
+
#ifdef CONFIG_FIQ
/**
* s3c24xx_set_fiq - set the FIQ routing
@@ -502,6 +553,13 @@ static struct s3c_irq_intc *s3c24xx_init_intc(struct device_node *np,
goto err;
}
+ if (address == 0x4a000000)
+ main_intc = intc;
+ else if (address == 0x4a000040)
+ main_intc2 = intc;
+
+ set_handle_irq(s3c24xx_handle_irq);
+
return intc;
err: