phy: rockchip-usb: correct pll handling and usb-uart
From: Heiko Stuebner <heiko@...> Date: Sun, 8 Nov 2015 16:23:27 +0100
changes in v2: - add Doug's review-tag to patches 1 and 3 - address comment and add the missing transistional rk_phy->base assignment in patch2 Patches 1-7 fix a long-standing issue with the clock-tree of Rockchip SoCs namely our ignorance of the usbphy-internal pll that creates the needed 480MHz but is also a supply-clock back to the core clock-controller in Rockchip SoCs. Till now that was worked around using a virtual clock in the cru itself, but that is of course ignorant of other parts then disabling the phy behind the cru's back, thus breaking potential users of these clocks. Patch 8, while not associated with the new pll handling, also builds on the groundwork introduced there and adds support for the function repurposing one of the phys as passthrough for uart-data. This enables attaching a ttl converter to the D+ and D- pins of an usb cable to receive uart data this way, when it is not really possible to attach a regular serial console to a board. One point of critique in my first iteration [0] of this was, that due to when the reconfiguration happens we may miss parts of the logs when earlycon is enabled. So far early_initcall gets used as the unflattened devicetree is necessary to set this up. Doing this for example in the early_param directly would require parsing the flattened devicetree to get needed nodes and properties. I still maintain that if you're working on anything before smp-bringup you should use a real dev-board instead or try to solder uart cables on hopefully available test-points :-) . In any case, if patch 8 causes to much headache, it could be dropped to not hinder the earlier 7 patches. [0] http://comments.gmane.org/gmane.linux.ports.arm.rockchip/715 Heiko Stuebner (8): phy: rockchip-usb: fix clock get-put mismatch phy: rockchip-usb: introduce a common data-struct for the device phy: rockchip-usb: move per-phy init into a separate function phy: rockchip-usb: expose the phy-internal PLLs clk: rockchip: fix usbphy-related clocks ARM: dts: rockchip: add clock-cells for usb phy nodes ARM: dts: rockchip: assign usbphy480m_src to the new usbphy pll on veyron phy: rockchip-usb: add handler for usb-uart functionality .../devicetree/bindings/phy/rockchip-usb-phy.txt | 6 +- Documentation/kernel-parameters.txt | 6 + arch/arm/boot/dts/rk3066a.dtsi | 2 + arch/arm/boot/dts/rk3188.dtsi | 2 + arch/arm/boot/dts/rk3288-veyron.dtsi | 2 +- arch/arm/boot/dts/rk3288.dtsi | 3 + drivers/clk/rockchip/clk-rk3188.c | 11 +- drivers/clk/rockchip/clk-rk3288.c | 16 +- drivers/phy/phy-rockchip-usb.c | 449 ++++++++++++++++++--- 9 files changed, 416 insertions(+), 81 deletions(-) -- 2.6.2
Patches in this set
- [0001] phy: rockchip-usb: fix clock get-put mismatch (raw)
- [0002] phy: rockchip-usb: introduce a common data-struct for the (raw)
- [0003] phy: rockchip-usb: move per-phy init into a separate (raw)
- [0004] phy: rockchip-usb: expose the phy-internal PLLs (raw)
- [0005] clk: rockchip: fix usbphy-related clocks (raw)
- [0006] ARM: dts: rockchip: add clock-cells for usb phy nodes (raw)
- [0007] ARM: dts: rockchip: assign usbphy480m_src to the new (raw)
- [0008] phy: rockchip-usb: add handler for usb-uart functionality (raw)
Statistics
- 8 individual patches
- 457 lines added
- 122 lines removed