ARM: dts: rockchip: convert rk3288 to operating-points-v2
From: Heiko Stuebner <heiko@...> Date: Sat, 16 Jun 2018 16:55:17 +0200
Commit-Message
Operating points need to be present in each cpu core using it, not only the first one. With operating-points-v1 this would require duplicating this table into each cpu node. With opp-v2 we can share the same table on all nodes. Signed-off-by: Heiko Stuebner <heiko@...>
Patch-Comment
arch/arm/boot/dts/rk3288-veyron.dtsi | 36 +++++++------- arch/arm/boot/dts/rk3288.dtsi | 70 ++++++++++++++++++++++------ 2 files changed, 75 insertions(+), 31 deletions(-)
Statistics
- 75 lines added
- 31 lines removed
Changes
--------------------- arch/arm/boot/dts/rk3288-veyron.dtsi ---------------------
index 823c7ed47fcf..c8c83bf544b9 100644
@@ -91,22 +91,26 @@
&cpu0 {
cpu0-supply = <&vdd_cpu>;
+};
+
+/* rk3288-c used in Veyron Chrome-devices has slightly changed OPPs */
+&cpu_opp_table {
+ /delete-node/ opp02;
+
+ opp10 {
+ opp-microvolt = <1250000>;
+ };
+ opp11 {
+ opp-microvolt = <1300000>;
+ };
+ opp12 {
+ opp-hz = /bits/ 64 <1704000000>;
+ opp-microvolt = <1350000>;
+ };
+ opp13 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <1400000>;
+ };
};
&emmc {
------------------------ arch/arm/boot/dts/rk3288.dtsi -------------------------
index 2a060c2dc383..a3af3f6ad8d0 100644
@@ -60,21 +60,7 @@
compatible = "arm,cortex-a12";
reg = <0x500>;
resets = <&cru SRST_CORE0>;
+ operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>; /* min followed by max */
clock-latency = <40000>;
clocks = <&cru ARMCLK>;
@@ -99,6 +85,60 @@
};
};
+ cpu_opp_table: cpu-opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <126000000>;
+ opp-microvolt = <900000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <216000000>;
+ opp-microvolt = <900000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <312000000>;
+ opp-microvolt = <900000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <900000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <900000>;
+ };
+ opp05 {
+ opp-hz = /bits/ 64 <696000000>;
+ opp-microvolt = <950000>;
+ };
+ opp06 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <1000000>;
+ };
+ opp07 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <1050000>;
+ };
+ opp08 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1100000>;
+ };
+ opp09 {
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <1200000>;
+ };
+ opp10 {
+ opp-hz = /bits/ 64 <1512000000>;
+ opp-microvolt = <1300000>;
+ };
+ opp11 {
+ opp-hz = /bits/ 64 <1608000000>;
+ opp-microvolt = <1350000>;
+ };
+ };
+
amba {
compatible = "simple-bus";
#address-cells = <2>;