PatchTrack

From: Heiko Stuebner <heiko@...> Date: Sun, 5 Dec 2021 12:01:49 +0100

Commit-Message

Svpbmt (the S should be capitalized) is the "Supervisor-mode: page-based memory types" extension that specifies attributes for cacheability, idempotency and ordering. The relevant settings are done in special bits in PTEs: Here is the svpbmt PTE format: | 63 | 62-61 | 60-8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 N MT RSW D A G U X W R V ^ Of the Reserved bits [63:54] in a leaf PTE, the high bit is already allocated (as the N bit), so bits [62:61] are used as the MT (aka MemType) field. This field specifies one of three memory types that are close equivalents (or equivalent in effect) to the three main x86 and ARMv8 memory types - as shown in the following table. RISC-V Encoding & MemType RISC-V Description ---------- ------------------------------------------------ 00 - PMA Normal Cacheable, No change to implied PMA memory type 01 - NC Non-cacheable, idempotent, weakly-ordered Main Memory 10 - IO Non-cacheable, non-idempotent, strongly-ordered I/O memory 11 - Rsvd Reserved for future standard use As the extension will not be present on all implementations, implement a method to handle cpufeatures via alternatives to not incur runtime penalties on cpu variants not supporting specific extensions and patch relevant code parts at runtime. Co-developed-by: Wei Fu <wefu@...> Signed-off-by: Wei Fu <wefu@...> Co-developed-by: Liu Shaohua <liush@...> Signed-off-by: Liu Shaohua <liush@...> Co-developed-by: Guo Ren <guoren@...> Signed-off-by: Guo Ren <guoren@...> [moved to use the alternatives mechanism] Signed-off-by: Heiko Stuebner <heiko@...> Cc: Christoph Hellwig <hch@...> Cc: Arnd Bergmann <arnd@...> Cc: Drew Fustini <drew@...> Cc: Wei Fu <wefu@...> Cc: Wei Wu <lazyparser@...> Cc: Chen-Yu Tsai <wens@...> Cc: Maxime Ripard <maxime@...> Cc: Daniel Lustig <dlustig@...> Cc: Greg Favor <gfavor@...> Cc: Andrea Mondelli <andrea.mondelli@...> Cc: Jonathan Behrens <behrensj@...> Cc: Xinhaoqu (Freddie) <xinhaoqu@...> Cc: Bill Huffman <huffman@...> Cc: Nick Kossifidis <mick@...> Cc: Allen Baum <allen.baum@...> Cc: Josh Scheid <jscheid@...> Cc: Richard Trauben <rtrauben@...>

Patch-Comment

arch/riscv/Kconfig | 13 +++++ arch/riscv/include/asm/alternative.h | 3 ++ arch/riscv/include/asm/errata_list.h | 15 ++++++ arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/include/asm/pgtable-32.h | 9 ++++ arch/riscv/include/asm/pgtable-64.h | 47 +++++++++++++++++ arch/riscv/include/asm/pgtable-bits.h | 4 -- arch/riscv/include/asm/pgtable.h | 29 +++++++++-- arch/riscv/kernel/alternative.c | 2 + arch/riscv/kernel/cpu.c | 1 + arch/riscv/kernel/cpufeature.c | 75 ++++++++++++++++++++++++++- 11 files changed, 189 insertions(+), 10 deletions(-)

Statistics

• 189 lines added
• 10 lines removed

Changes