SVPBMT + T-Head memory types next try

A patchset in state Mainline for linux-kernel

From: Heiko Stuebner <heiko@...> Date: Thu, 13 Jan 2022 00:15:26 +0100

Hi, so this is my next try at solving this. As suggested by Nick, I've moved the PMA type away into a form where the T-Head errata just looks for "no other memory type set" and then sets the pma type if needed. I've left the _IO and _NOCACHE variants + MTMASK as is, as * PAGE_IOREMAP is actually needed by the "generic" ioremap implementation * _PAGE_CHG_MASK needs the PBMT bits as well * it reduces the number places we hack up I've also reduced the number of alternatives-stages by simply moving the boot stage to the front a bit and removing my "early" stage. As said in the previous thread and in [0] fdt functions are "kasan instrumented" so I kept the 2 stages vm+boot for the strange things (vm) and regular erratas (boot). I've tested this on 5.16-rc8 with Atish's sparse-hartid set applied (affects the sbi patch) on qemu+svpbmt patchset and D1-Nezha, as well as the D1 on Samuel Holland's D1 tree that enables the board to boot to a prompt (on my Debian rootfs). [The patches have kept their original authors as shown in the shortlog, I've just changed the authorship in the individual patches to not confuse git-send-email and send mails to people I don't want to involve yet ;-) ] [0] https://lore.kernel.org/all/20211206104657.433304-14-alexandre.ghiti@canonical.com/ Guo Ren (1): riscv: Fixup _PAGE_CHG_MASK usage in pgtable Heiko Stuebner (11): riscv: prevent null-pointer dereference with sbi_remote_fence_i riscv: integrate alternatives better into the main architecture riscv: allow different stages with alternatives riscv: implement module alternatives riscv: implement ALTERNATIVE_2 macro riscv: extend concatenated alternatives-lines to the same length riscv: prevent compressed instructions in alternatives riscv: move boot alternatives to a slightly earlier position riscv: add cpufeature handling via alternatives riscv: remove FIXMAP_PAGE_IO and fall back to its default value riscv: add memory-type errata for T-Head Wei Fu (2): dt-bindings: riscv: add MMU Standard Extensions support for Svpbmt riscv: add RISC-V Svpbmt extension supports .../devicetree/bindings/riscv/cpus.yaml | 10 ++ arch/riscv/Kconfig.erratas | 29 ++-- arch/riscv/Kconfig.socs | 1 - arch/riscv/Makefile | 2 +- arch/riscv/errata/Makefile | 2 +- arch/riscv/errata/sifive/errata.c | 10 +- arch/riscv/errata/thead/Makefile | 1 + arch/riscv/errata/thead/errata.c | 85 +++++++++++ arch/riscv/include/asm/alternative-macros.h | 114 ++++++++------- arch/riscv/include/asm/alternative.h | 16 ++- arch/riscv/include/asm/errata_list.h | 52 +++++++ arch/riscv/include/asm/fixmap.h | 2 - arch/riscv/include/asm/pgtable-32.h | 9 ++ arch/riscv/include/asm/pgtable-64.h | 73 +++++++++- arch/riscv/include/asm/pgtable-bits.h | 4 - arch/riscv/include/asm/pgtable.h | 53 +++++-- arch/riscv/include/asm/vendorid_list.h | 1 + arch/riscv/kernel/Makefile | 1 + arch/riscv/{errata => kernel}/alternative.c | 47 +++++- arch/riscv/kernel/cpufeature.c | 135 +++++++++++++++++- arch/riscv/kernel/module.c | 29 ++++ arch/riscv/kernel/sbi.c | 10 +- arch/riscv/kernel/smpboot.c | 4 - arch/riscv/kernel/soc.c | 3 + arch/riscv/kernel/traps.c | 2 +- arch/riscv/mm/cacheflush.c | 15 +- arch/riscv/mm/init.c | 2 + 27 files changed, 605 insertions(+), 107 deletions(-) create mode 100644 arch/riscv/errata/thead/Makefile create mode 100644 arch/riscv/errata/thead/errata.c rename arch/riscv/{errata => kernel}/alternative.c (60%) -- 2.30.2

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