dt-bindings: riscv: add MMU Standard Extensions support
From: Wei Fu <wefu@...> Date: Mon, 29 Nov 2021 09:40:06 +0800
Commit-Message
Previous patch has added svpbmt in arch/riscv and add "riscv,svpmbt" in the DT mmu node. Update dt-bindings related property here. Signed-off-by: Wei Fu <wefu@...> Co-developed-by: Guo Ren <guoren@...> Signed-off-by: Guo Ren <guoren@...> Signed-off-by: Heiko Stuebner <heiko@...>
Patch-Comment
Documentation/devicetree/bindings/riscv/cpus.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+)
Statistics
- 10 lines added
- 0 lines removed
Changes
-------------- Documentation/devicetree/bindings/riscv/cpus.yaml ---------------
index aa5fb64d57eb..3ad2593f1400 100644
@@ -63,6 +63,16 @@ properties:
- riscv,sv48
- riscv,none
+ mmu:
+ description:
+ Describes the CPU's MMU Standard Extensions support.
+ These values originate from the RISC-V Privileged
+ Specification document, available from
+ https://riscv.org/specifications/
+ $ref: '/schemas/types.yaml#/definitions/string'
+ enum:
+ - riscv,svpbmt
+
riscv,isa:
description:
Identifies the specific RISC-V instruction set architecture