RISC-V: add U-type imm parsing to parse_asm header
From: Heiko Stuebner <heiko@...> Date: Tue, 1 Nov 2022 14:09:56 +0100
Commit-Message
Similar to other existing types, allow extracting the immediate for a U-type instruction. U-type immediates are special in that regard, that the value in the instruction in bits [31:12] already represents the same bits of the immediate, so no shifting is required. Signed-off-by: Heiko Stuebner <heiko@...>
Patch-Comment
arch/riscv/include/asm/parse_asm.h | 13 +++++++++++++ 1 file changed, 13 insertions(+)
Statistics
- 13 lines added
- 0 lines removed
Changes
---------------------- arch/riscv/include/asm/parse_asm.h ----------------------
index c287c1426aa7..939ede0ee527 100644
@@ -25,6 +25,15 @@
#define J_IMM_11_MASK GENMASK(0, 0)
#define J_IMM_19_12_MASK GENMASK(7, 0)
+/*
+ * U-type IMMs contain the upper 20bits [31:20] of an immediate with
+ * the rest filled in by zeros, so no shifting required. Similarly,
+ * bit31 contains the signed state, so no sign extension necessary.
+ */
+#define U_IMM_SIGN_OPOFF 31
+#define U_IMM_31_12_OPOFF 0
+#define U_IMM_31_12_MASK GENMASK(31, 12)
+
/* The bit field of immediate value in B-type instruction */
#define B_IMM_SIGN_OPOFF 31
#define B_IMM_10_5_OPOFF 25
@@ -183,6 +192,10 @@ static inline bool is_ ## INSN_NAME ## _insn(long insn) \
#define RV_X(X, s, mask) (((X) >> (s)) & (mask))
#define RVC_X(X, s, mask) RV_X(X, s, mask)
+#define EXTRACT_UTYPE_IMM(x) \
+ ({typeof(x) x_ = (x); \
+ (RV_X(x_, U_IMM_31_12_OPOFF, U_IMM_31_12_MASK)); })
+
#define EXTRACT_JTYPE_IMM(x) \
({typeof(x) x_ = (x); \
(RV_X(x_, J_IMM_10_1_OPOFF, J_IMM_10_1_MASK) << J_IMM_10_1_OFF) | \