dt-bindings: riscv: document cbom-block-size
From: Heiko Stuebner <heiko@...> Date: Fri, 6 May 2022 16:18:33 +0200
Commit-Message
The Zicbom operates on a block-size defined for the cpu-core, which does not necessarily match other cache-sizes used. So add the necessary property for the system to know the core's block-size. Reviewed-by: Anup Patel <anup@...> Reviewed-by: Guo Ren <guoren@...> Acked-by: Rob Herring <robh@...> Signed-off-by: Heiko Stuebner <heiko@...>
Patch-Comment
Documentation/devicetree/bindings/riscv/cpus.yaml | 5 +++++ 1 file changed, 5 insertions(+)
Statistics
- 5 lines added
- 0 lines removed
Changes
-------------- Documentation/devicetree/bindings/riscv/cpus.yaml ---------------
index d632ac76532e..873dd12f6e89 100644
@@ -63,6 +63,11 @@ properties:
- riscv,sv48
- riscv,none
+ riscv,cbom-block-size:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ The blocksize in bytes for the Zicbom cache operations.
+
riscv,isa:
description:
Identifies the specific RISC-V instruction set architecture