dt-bindings: display: rockchip-dsi: document external
From: Heiko Stuebner <heiko.stuebner@...> Date: Fri, 8 Nov 2019 00:34:37 +0100
Commit-Message
Some dw-mipi-dsi instances in Rockchip SoCs use external dphys. In these cases the needs clock will also be generated externally so these don't need the ref-clock as well. Signed-off-by: Heiko Stuebner <heiko.stuebner@...>
Patch-Comment
.../bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)
Statistics
- 5 lines added
- 2 lines removed
Changes
- Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt --
index ce4c1fc9116c..1ba9237d0ac0 100644
@@ -9,8 +9,9 @@ Required properties:
- reg: Represent the physical address range of the controller.
- interrupts: Represent the controller's interrupt to the CPU(s).
- clocks, clock-names: Phandles to the controller's pll reference
+ clock(ref) when using an internal dphy and APB clock(pclk).
+ For RK3399, a phy config clock (phy_cfg) and a grf clock(grf)
+ are required. As described in [1].
- rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
- ports: contain a port node with endpoint definitions as defined in [2].
For vopb,set the reg = <0> and set the reg = <1> for vopl.
@@ -18,6 +19,8 @@ Required properties:
- video port 1 for either a panel or subsequent encoder
Optional properties:
+- phys: from general PHY binding: the phandle for the PHY device.
+- phy-names: Should be "dphy" if phys references an external phy.
- power-domains: a phandle to mipi dsi power domain node.
- resets: list of phandle + reset specifier pairs, as described in [3].
- reset-names: string reset name, must be "apb".