arm64: dts: rockchip: add PCIe3 support on rk3588-jaguar
From: Heiko Stuebner <heiko.stuebner@...> Date: Tue, 14 Nov 2023 16:27:22 +0100
Commit-Message
The Jaguar SBC provides a M.2 slot connected to the pcie3 controller. In contrast to a number of other boards the pcie-refclk is gpio-controlled, so the necessary clock is added to the list of pcie3 clocks. Signed-off-by: Heiko Stuebner <heiko.stuebner@...>
Patch-Comment
.../arm64/boot/dts/rockchip/rk3588-jaguar.dts | 53 +++++++++++++++++++ 1 file changed, 53 insertions(+)
Statistics
- 53 lines added
- 0 lines removed
Changes
---------------- arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts ----------------
index 5002105dc78e..908fbabd8b00 100644
@@ -72,6 +72,25 @@ led-1 {
};
};
+ /*
+ * 100MHz reference clock for PCIe peripherals from PI6C557-05BLE
+ * clock generator.
+ * The clock output is gated via the OE pin on the clock generator.
+ * This is modeled as a fixed-clock plus a gpio-gate-clock.
+ */
+ pcie_refclk_gen: pcie-refclk-gen-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1000000000>;
+ };
+
+ pcie_refclk: pcie-refclk-clock {
+ compatible = "gpio-gate-clock";
+ clocks = <&pcie_refclk_gen>;
+ #clock-cells = <0>;
+ enable-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>; /* PCIE30X4_CLKREQN_M0 */
+ };
+
pps {
compatible = "pps-gpio";
gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
@@ -466,6 +485,40 @@ &pcie2x1l0 {
status = "okay";
};
+&pcie30phy {
+ status = "okay";
+};
+
+&pcie30x4m0_pins {
+ /*
+ * pcie30x4_clkreqn_m0 is used by the refclk generator
+ * pcie30x4_perstn_m0 is used as via the reset-gpio
+ */
+ rockchip,pins =
+ /* pcie30x4_waken_m0 */
+ <0 RK_PC7 12 &pcfg_pull_none>;
+};
+
+&pcie3x4 {
+ /*
+ * The board has a gpio-controlled "pcie_refclk" generator,
+ * so add it to the list of clocks.
+ */
+ clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
+ <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
+ <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>,
+ <&pcie_refclk>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk",
+ "aux", "pipe",
+ "ref";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie30x4m0_pins>;
+ reset-gpios = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>; /* PCIE30X4_PERSTN_M0 */
+ vpcie3v3-supply = <&vcc3v3_mdot2>;
+ status = "okay";
+};
+
&pinctrl {
emmc {
emmc_reset: emmc-reset {