clk: rockchip: add a type from SGRF-controlled gate
From: Heiko Stuebner <heiko@...> Date: Thu, 6 Jun 2019 10:05:40 +0200
Commit-Message
Some clk gates on Rockchip SoCs are part of the SGRF (secure general register files) and thus only controllable from secure mode, with the most prominent example being the watchdog. In most cases we still want to define this as a real clock though, to have complete clock tree and not reference the generic base-clock from the devicetree. So far we've just defined this as factor-1-1 clocks in the clock init, so define a special clock-type for it so that this definition can be part of the general tree-definition and save some boilerplate code. Signed-off-by: Heiko Stuebner <heiko@...>
Patch-Comment
drivers/clk/rockchip/clk.h | 4 ++++ 1 file changed, 4 insertions(+)
Statistics
- 4 lines added
- 0 lines removed
Changes
-------------------------- drivers/clk/rockchip/clk.h --------------------------
index 1b5270755431..2a911923cf81 100644
@@ -820,6 +820,10 @@ struct rockchip_clk_branch {
.gate_offset = -1, \
}
+/* SGRF clocks are only accessible from secure mode, so not controllable */
+#define SGRF_GATE(_id, cname, pname) \
+ FACTOR(_id, cname, pname, 0, 1, 1)
+
struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np,
void __iomem *base, unsigned long nr_clks);
void rockchip_clk_of_add_provider(struct device_node *np,