RISC-V: move vector-available status into a dedicated
From: Heiko Stuebner <heiko.stuebner@...> Date: Wed, 15 Mar 2023 11:47:45 +0100
Commit-Message
There is at least one core implementing the wrong vector specification, which cannot claim to implement the v extension but still is able to do vectors similar to v. To not hack around this by claiming to do v, move the has_vector() return to act similar to riscv_noncoherent_supported() and move to a separate variable that can be set for example from errata code. Signed-off-by: Heiko Stuebner <heiko.stuebner@...>
Patch-Comment
arch/riscv/include/asm/vector.h | 5 ++++- arch/riscv/kernel/setup.c | 6 ++++++ arch/riscv/kernel/vector.c | 8 ++++++++ 3 files changed, 18 insertions(+), 1 deletion(-)
Statistics
- 18 lines added
- 1 lines removed
Changes
----------------------- arch/riscv/include/asm/vector.h ------------------------
index 04c0b07bf6cd..315c96d2b4d0 100644
@@ -19,13 +19,16 @@
#include <asm/csr.h>
#include <asm/asm.h>
+extern bool riscv_v_supported;
+void riscv_vector_supported(void);
+
extern unsigned long riscv_v_vsize;
int riscv_v_setup_vsize(void);
bool riscv_v_first_use_handler(struct pt_regs *regs);
static __always_inline bool has_vector(void)
{
+ return riscv_v_supported;
}
static inline void __riscv_v_vstate_clean(struct pt_regs *regs)
-------------------------- arch/riscv/kernel/setup.c ---------------------------
index 971fe776e2f8..952dfb90525e 100644
@@ -36,6 +36,7 @@
#include <asm/thread_info.h>
#include <asm/kasan.h>
#include <asm/efi.h>
+#include <asm/vector.h>
#include "head.h"
@@ -308,6 +309,11 @@ void __init setup_arch(char **cmdline_p)
riscv_fill_hwcap();
init_rt_signal_env();
apply_boot_alternatives();
+
+ if (IS_ENABLED(CONFIG_RISCV_ISA_V) &&
+ riscv_isa_extension_available(NULL, v))
+ riscv_vector_supported();
+
if (IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM) &&
riscv_isa_extension_available(NULL, ZICBOM))
riscv_noncoherent_supported();
-------------------------- arch/riscv/kernel/vector.c --------------------------
index f9c8e19ab301..74178fb71805 100644
@@ -22,6 +22,9 @@
static bool riscv_v_implicit_uacc = IS_ENABLED(CONFIG_RISCV_ISA_V_DEFAULT_ENABLE);
+bool riscv_v_supported;
+EXPORT_SYMBOL_GPL(riscv_v_supported);
+
unsigned long riscv_v_vsize __read_mostly;
EXPORT_SYMBOL_GPL(riscv_v_vsize);
@@ -274,3 +277,8 @@ static int riscv_v_init(void)
return riscv_v_sysctl_init();
}
core_initcall(riscv_v_init);
+
+void riscv_vector_supported(void)
+{
+ riscv_v_supported = true;
+}