clk: handle fixed-rate clocks correctly in clk_core_round_rate_nolock
From: Heiko Stuebner <heiko@...> Date: Sun, 26 Jul 2015 00:03:47 +0200
Commit-Message
Commit 6edc753d8ecc ("clk: change clk_ops' ->determine_rate() prototype") changed the behaviour of clk_core_round_rate_nolock as it forgot to also include the else conditional simply returning the clock rate for clocks that neither have a parent or can determine their rate - for example said fixed clocks. This resulted in failures to set pll rates on rockchip socs, as it returned the target pll rate as suitable rate for the 24MHz xin24m clock, thus making the ccf want to set this fixed clock to 1.6GHz or similar. Fixes: 6edc753d8ecc ("clk: change clk_ops' ->determine_rate() prototype") Reported-by: Romain Perier <romain.perier@...> Signed-off-by: Heiko Stuebner <heiko@...>
Patch-Comment
###### was merged into the original offending commit ###### drivers/clk/clk.c | 2 ++ 1 file changed, 2 insertions(+)
Statistics
- 2 lines added
- 0 lines removed