clk: rk3288: limit gpll and cpll init to SPL build
From: Heiko Stuebner <heiko@...> Date: Sat, 18 Feb 2017 15:03:16 +0100
Commit-Message
The gpll and cpll init values are only used in rk_clk_init in the SPL and therefore produce compile time warnings in regular uboot builds. Fix that with an #ifdef. Signed-off-by: Heiko Stuebner <heiko@...>
Patch-Comment
drivers/clk/rockchip/clk_rk3288.c | 2 ++ 1 file changed, 2 insertions(+)
Statistics
- 2 lines added
- 0 lines removed
Changes
---------------------- drivers/clk/rockchip/clk_rk3288.c -----------------------
index d15504c3aa..78356766a7 100644
@@ -131,8 +131,10 @@ enum {
/* Keep divisors as low as possible to reduce jitter and power usage */
static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
+#ifdef CONFIG_SPL_BUILD
static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
+#endif
static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
const struct pll_div *div)