rockchip: px30: enable spl-fifo-mode for both emmc and
From: Heiko Stuebner <heiko.stuebner@...> Date: Mon, 18 Nov 2019 15:01:53 +0100
Commit-Message
As part of loading trustedfirmware, the SPL is required to place portions of code into the socs sram but the mmc controllers can only do dma transfers into the regular memory, not sram. The results of this are not directly visible in u-boot itself, but manifest as security-relate cpu aborts during boot of for example Linux. There were a number of attempts to solve this elegantly but so far discussion is still ongoing, so to make the board at least boot correctly put both mmc controllers into fifo-mode, which also circumvents the issue for now. Signed-off-by: Heiko Stuebner <heiko.stuebner@...>
Patch-Comment
changes in v2: - moved to a spl-specific property, as suggested by Philipp arch/arm/dts/px30-evb-u-boot.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)
Statistics
- 5 lines added
- 2 lines removed