spi-s3c64xx: make spi baseclock configurable
From: Heiko Stuebner <heiko.stuebner@...> Date: Thu, 19 Jan 2012 11:36:55 +0100
Commit-Message
SoCs like the S3C2443 contain both a spi controller compatible with spi-s3c24xx and another hsspi controller compatible with spi-s3c64xx. Therefore they also use two different clocks "spi" for the first and "hsspi" for the second controller. This patch makes the spi clock the spi-s3c64xx driver should use configurable to support thios scenario. Signed-off-by: Heiko Stuebner <heiko@...>
Patch-Comment
drivers/spi/spi-s3c64xx.c | 9 ++++++--- include/linux/spi/s3c64xx.h | 2 ++ 2 files changed, 8 insertions(+), 3 deletions(-)
Statistics
- 8 lines added
- 3 lines removed
Changes
-------------------------- drivers/spi/spi-s3c64xx.c ---------------------------
index e30006d..22ab706 100644
@@ -972,6 +972,7 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev)
struct spi_master *master;
int ret;
char clk_name[16];
+ char *spiclk;
if (pdev->id < 0) {
dev_err(&pdev->dev,
@@ -1055,16 +1056,18 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev)
goto err2;
}
+ spiclk = sci->spiclk_name ? sci->spiclk_name : "spi";
+
/* Setup clocks */
+ sdd->clk = clk_get(&pdev->dev, spiclk);
if (IS_ERR(sdd->clk)) {
+ dev_err(&pdev->dev, "Unable to acquire clock '%s'\n", spiclk);
ret = PTR_ERR(sdd->clk);
goto err3;
}
if (clk_enable(sdd->clk)) {
+ dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", spiclk);
ret = -EBUSY;
goto err4;
}
------------------------- include/linux/spi/s3c64xx.h --------------------------
index 31cf023..358ff8e 100644
@@ -34,6 +34,7 @@ struct s3c64xx_spi_csinfo {
* @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field.
* @clk_from_cmu: If the SPI clock/prescalar control block is present
* by the platform's clock-management-unit and not in SPI controller.
+ * @spiclk_name: name of the base spi clock, if unset "spi" is used
* @num_cs: Number of CS this controller emulates.
* @cfg_gpio: Configure pins for this SPI controller.
* @fifo_lvl_mask: All tx fifo_lvl fields start at offset-6
@@ -44,6 +45,7 @@ struct s3c64xx_spi_csinfo {
struct s3c64xx_spi_info {
int src_clk_nr;
bool clk_from_cmu;
+ char *spiclk_name;
int num_cs;