RISC-V: add vector crypto extension detection

A patch from »RISC-V: support some cryptography accelerations« in state Obsolete for linux-kernel

From: Heiko Stuebner <heiko.stuebner@...> Date: Tue, 31 Jan 2023 11:52:46 +0100

Commit-Message

Add detection for some extensions of the vector-crypto specification, namely - Zvkb: Vector Bit-manipulation used in Cryptography - Zvkg: Vector GCM/GMAC - Zvknha and Zvknhb: NIST Algorithm Suite - Zvkns: AES-128, AES-256 Single Round Suite - Zvksed: ShangMi Algorithm Suite - Zvksh: ShangMi Algorithm Suite As their use is very specific and will likely be limited to special places we expect current code to just pre-encode those instructions, so right now we don't introduce toolchain requirements. Signed-off-by: Heiko Stuebner <heiko.stuebner@...>

Patch-Comment

arch/riscv/include/asm/hwcap.h | 7 +++++++ arch/riscv/kernel/cpu.c | 7 +++++++ arch/riscv/kernel/cpufeature.c | 7 +++++++ 3 files changed, 21 insertions(+)

Statistics

  • 21 lines added
  • 0 lines removed

Changes

------------------------ arch/riscv/include/asm/hwcap.h ------------------------
index b28548fb10f3..914559e0e136 100644
@@ -45,6 +45,13 @@
#define RISCV_ISA_EXT_ZIHINTPAUSE 32
#define RISCV_ISA_EXT_ZBC 33
#define RISCV_ISA_EXT_ZBKB 34
+#define RISCV_ISA_EXT_ZVKB 35
+#define RISCV_ISA_EXT_ZVKG 36
+#define RISCV_ISA_EXT_ZVKNED 37
+#define RISCV_ISA_EXT_ZVKNHA 38
+#define RISCV_ISA_EXT_ZVKNHB 39
+#define RISCV_ISA_EXT_ZVKSED 40
+#define RISCV_ISA_EXT_ZVKSH 41
#define RISCV_ISA_EXT_MAX 64
#define RISCV_ISA_EXT_NAME_LEN_MAX 32
--------------------------- arch/riscv/kernel/cpu.c ----------------------------
index 6f65aac68018..c01e6673a947 100644
@@ -190,6 +190,13 @@ static struct riscv_isa_ext_data isa_ext_arr[] = {
__RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
__RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC),
__RISCV_ISA_EXT_DATA(zbkb, RISCV_ISA_EXT_ZBKB),
+ __RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB),
+ __RISCV_ISA_EXT_DATA(zvkg, RISCV_ISA_EXT_ZVKG),
+ __RISCV_ISA_EXT_DATA(zvkned, RISCV_ISA_EXT_ZVKNED),
+ __RISCV_ISA_EXT_DATA(zvknha, RISCV_ISA_EXT_ZVKNHA),
+ __RISCV_ISA_EXT_DATA(zvknhb, RISCV_ISA_EXT_ZVKNHB),
+ __RISCV_ISA_EXT_DATA(zvksed, RISCV_ISA_EXT_ZVKSED),
+ __RISCV_ISA_EXT_DATA(zvksh, RISCV_ISA_EXT_ZVKSH),
__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
__RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
__RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
------------------------ arch/riscv/kernel/cpufeature.c ------------------------
index eb7be8e7f24e..ad866321ae37 100644
@@ -232,6 +232,13 @@ void __init riscv_fill_hwcap(void)
SET_ISA_EXT_MAP("zbkb", RISCV_ISA_EXT_ZBKB);
SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM);
SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE);
+ SET_ISA_EXT_MAP("zvkb", RISCV_ISA_EXT_ZVKB);
+ SET_ISA_EXT_MAP("zvkg", RISCV_ISA_EXT_ZVKG);
+ SET_ISA_EXT_MAP("zvkned", RISCV_ISA_EXT_ZVKNED);
+ SET_ISA_EXT_MAP("zvknha", RISCV_ISA_EXT_ZVKNHA);
+ SET_ISA_EXT_MAP("zvknhb", RISCV_ISA_EXT_ZVKNHB);
+ SET_ISA_EXT_MAP("zvksed", RISCV_ISA_EXT_ZVKSED);
+ SET_ISA_EXT_MAP("zvksh", RISCV_ISA_EXT_ZVKSH);
}
#undef SET_ISA_EXT_MAP
}
 
 

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