RISC-V: add cpufeature probing for fast-unaligned access
From: Heiko Stuebner <heiko.stuebner@...> Date: Wed, 11 Jan 2023 15:34:03 +0100
Commit-Message
Use the recently added misaligned access descriptor and derive a cpufeature id from it so that it can be used in alternative patches. We assume slow unaligned access if any cpu-core does not support fast access. Signed-off-by: Heiko Stuebner <heiko.stuebner@...>
Patch-Comment
arch/riscv/include/asm/errata_list.h | 9 +++++---- arch/riscv/kernel/cpufeature.c | 20 ++++++++++++++++++++ 2 files changed, 25 insertions(+), 4 deletions(-)
Statistics
- 25 lines added
- 4 lines removed
Changes
--------------------- arch/riscv/include/asm/errata_list.h ---------------------
index 043b79c79824..6ce0c22ae994 100644
@@ -22,10 +22,11 @@
#define ERRATA_THEAD_NUMBER 3
#endif
+#define CPUFEATURE_SVPBMT (1 << 0)
+#define CPUFEATURE_ZICBOM (1 << 1)
+#define CPUFEATURE_ZBB (1 << 2)
+#define CPUFEATURE_FAST_UNALIGNED (1 << 3)
+#define CPUFEATURE_NUMBER 4
#ifdef __ASSEMBLY__
------------------------ arch/riscv/kernel/cpufeature.c ------------------------
index a65bebdadb68..640b78f6aaa9 100644
@@ -337,6 +337,23 @@ static bool __init_or_module cpufeature_probe_zbb(unsigned int stage)
return true;
}
+static bool __init_or_module cpufeature_probe_fast_unaligned(unsigned int stage)
+{
+ int cpu;
+
+ if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
+ return false;
+
+ for_each_possible_cpu(cpu) {
+ long perf = per_cpu(misaligned_access_speed, cpu);
+
+ if (perf != RISCV_HWPROBE_MISALIGNED_FAST)
+ return false;
+ }
+
+ return true;
+}
+
/*
* Probe presence of individual extensions.
*
@@ -358,6 +375,9 @@ static u32 __init_or_module cpufeature_probe(unsigned int stage)
if (cpufeature_probe_zbb(stage))
cpu_req_feature |= CPUFEATURE_ZBB;
+ if (cpufeature_probe_fast_unaligned(stage))
+ cpu_req_feature |= CPUFEATURE_FAST_UNALIGNED;
+
return cpu_req_feature;
}