dt-bindings: Add documentation for rockchip lvds
From: Mark Yao <yzq@...> Date: Tue, 28 Oct 2014 10:00:18 +0800
Commit-Message
Add binding documentation for Rockchip SoC LVDS driver. Signed-off-by: Mark Yao <yzq@...> Signed-off-by: Heiko Stuebner <heiko@...>
Patch-Comment
.../devicetree/bindings/video/rockchip-lvds.txt | 59 ++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/video/rockchip-lvds.txt
Statistics
- 59 lines added
- 0 lines removed
Changes
---------- Documentation/devicetree/bindings/video/rockchip-lvds.txt -----------
new file mode 100644
index 0000000..1616d7e
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+Rockchip RK3288 LVDS interface
+================================
+
+Required properties:
+- compatible: "rockchip,rk3288-lvds";
+
+- reg: physical base address of the controller and length
+ of memory mapped region.
+- clocks: must include clock specifiers corresponding to entries in the
+ clock-names property.
+- clock-names: must contain "pclk_lvds"
+
+- avdd1v0-supply: regulator phandle for 1.0V analog power
+- avdd1v8-supply: regulator phandle for 1.8V analog power
+- avdd3v3-supply: regulator phandle for 3.3V analog power
+
+- rockchip,grf: phandle to the general register files syscon
+- rockchip,panel: phandle to a panel node as described by
+ Documentation/devicetree/bindings/panel/*
+
+- rockchip,data-mapping: should be "vesa" or "jeida",
+ This describes how the color bits are laid out in the
+ serialized LVDS signal.
+- rockchip,data-width : should be <18> or <24>;
+- rockchip,output: should be "rgb", "lvds" or "duallvds",
+ This describes the output face.
+
+- ports: contain a port node with endpoint definitions as defined in
+ Documentation/devicetree/bindings/media/video-interfaces.txt.
+
+Example:
+ lvds: lvds@ff96c000 {
+ compatible = "rockchip,rk3288-lvds";
+ rockchip,grf = <&grf>;
+ reg = <0xff96c000 0x4000>;
+ clocks = <&cru PCLK_LVDS_PHY>;
+ clock-names = "pclk_lvds";
+ avdd1v0-supply = <&vdd10_lcd>;
+ avdd1v8-supply = <&vcc18_lcd>;
+ avdd3v3-supply = <&vcca_33>;
+ rockchip,panel = <&panel>;
+ rockchip,data-mapping = "jeida";
+ rockchip,data-width = <24>;
+ rockchip,output = "rgb";
+ ports {
+ lvds_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ lvds_in_vopb: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vopb_out_lvds>;
+ };
+ lvds_in_vopl: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vopl_out_lvds>;
+ };
+ };
+ };
+ };