rockchip: add core px30 headers
From: Heiko Stuebner <heiko@...> Date: Tue, 16 Jul 2019 22:17:13 +0200
Commit-Message
Add headers needed by the upcoming px30 support, including two new dt-binding headers taken from the Linux kernel. Signed-off-by: Heiko Stuebner <heiko.stuebner@...>
Patch-Comment
arch/arm/include/asm/arch-rockchip/grf_px30.h | 144 ++++++++++++++++++ include/configs/px30_common.h | 62 ++++++++ include/dt-bindings/power/px30-power.h | 27 ++++ include/dt-bindings/soc/rockchip,boot-mode.h | 16 ++ 4 files changed, 249 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/grf_px30.h create mode 100644 include/configs/px30_common.h create mode 100644 include/dt-bindings/power/px30-power.h create mode 100644 include/dt-bindings/soc/rockchip,boot-mode.h
Statistics
- 249 lines added
- 0 lines removed
Changes
---------------- arch/arm/include/asm/arch-rockchip/grf_px30.h -----------------
new file mode 100644
index 0000000000..c167bb42fa
@@ -0,0 +1,144 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
+ */
+#ifndef _ASM_ARCH_GRF_px30_H
+#define _ASM_ARCH_GRF_px30_H
+
+#include <common.h>
+
+struct px30_grf {
+ unsigned int gpio1al_iomux;
+ unsigned int gpio1ah_iomux;
+ unsigned int gpio1bl_iomux;
+ unsigned int gpio1bh_iomux;
+ unsigned int gpio1cl_iomux;
+ unsigned int gpio1ch_iomux;
+ unsigned int gpio1dl_iomux;
+ unsigned int gpio1dh_iomux;
+
+ unsigned int gpio2al_iomux;
+ unsigned int gpio2ah_iomux;
+ unsigned int gpio2bl_iomux;
+ unsigned int gpio2bh_iomux;
+ unsigned int gpio2cl_iomux;
+ unsigned int gpio2ch_iomux;
+ unsigned int gpio2dl_iomux;
+ unsigned int gpio2dh_iomux;
+
+ unsigned int gpio3al_iomux;
+ unsigned int gpio3ah_iomux;
+ unsigned int gpio3bl_iomux;
+ unsigned int gpio3bh_iomux;
+ unsigned int gpio3cl_iomux;
+ unsigned int gpio3ch_iomux;
+ unsigned int gpio3dl_iomux;
+ unsigned int gpio3dh_iomux;
+
+ unsigned int gpio1a_p;
+ unsigned int gpio1b_p;
+ unsigned int gpio1c_p;
+ unsigned int gpio1d_p;
+ unsigned int gpio2a_p;
+ unsigned int gpio2b_p;
+ unsigned int gpio2c_p;
+ unsigned int gpio2d_p;
+ unsigned int gpio3a_p;
+ unsigned int gpio3b_p;
+ unsigned int gpio3c_p;
+ unsigned int gpio3d_p;
+ unsigned int gpio1a_sr;
+ unsigned int gpio1b_sr;
+ unsigned int gpio1c_sr;
+ unsigned int gpio1d_sr;
+ unsigned int gpio2a_sr;
+ unsigned int gpio2b_sr;
+ unsigned int gpio2c_sr;
+ unsigned int gpio2d_sr;
+ unsigned int gpio3a_sr;
+ unsigned int gpio3b_sr;
+ unsigned int gpio3c_sr;
+ unsigned int gpio3d_sr;
+ unsigned int gpio1a_smt;
+ unsigned int gpio1b_smt;
+ unsigned int gpio1c_smt;
+ unsigned int gpio1d_smt;
+ unsigned int gpio2a_smt;
+ unsigned int gpio2b_smt;
+ unsigned int gpio2c_smt;
+ unsigned int gpio2d_smt;
+ unsigned int gpio3a_smt;
+ unsigned int gpio3b_smt;
+ unsigned int gpio3c_smt;
+ unsigned int gpio3d_smt;
+ unsigned int gpio1a_e;
+ unsigned int gpio1b_e;
+ unsigned int gpio1c_e;
+ unsigned int gpio1d_e;
+ unsigned int gpio2a_e;
+ unsigned int gpio2b_e;
+ unsigned int gpio2c_e;
+ unsigned int gpio2d_e;
+ unsigned int gpio3a_e;
+ unsigned int gpio3b_e;
+ unsigned int gpio3c_e;
+ unsigned int gpio3d_e;
+
+ unsigned int reserved0[(0x180 - 0x11C) / 4 - 1];
+ unsigned int io_vsel;
+ unsigned int iofunc_con0;
+ unsigned int reserved1[(0x400 - 0x184) / 4 - 1];
+ unsigned int soc_con[6];
+ unsigned int reserved2[(0x480 - 0x414) / 4 - 1];
+ unsigned int soc_status0;
+ unsigned int reserved3[(0x500 - 0x480) / 4 - 1];
+ unsigned int cpu_con[3];
+ unsigned int reserved4[5];
+ unsigned int cpu_status[2];
+ unsigned int reserved5[2];
+ unsigned int soc_noc_con[2];
+ unsigned int reserved6[6];
+ unsigned int ddr_bankhash[4];
+ unsigned int reserved7[(0x700 - 0x55c) / 4 - 1];
+ unsigned int host0_con[2];
+ unsigned int reserved8[(0x880 - 0x704) / 4 - 1];
+ unsigned int otg_con3;
+ unsigned int reserved9[3];
+ unsigned int host0_status4;
+ unsigned int reserved10[(0x904 - 0x890) / 4 - 1];
+ unsigned int mac_con1;
+};
+
+check_member(px30_grf, mac_con1, 0x904);
+
+struct px30_pmugrf {
+ unsigned int gpio0a_e;
+ unsigned int gpio0b_e;
+ unsigned int gpio0c_e;
+ unsigned int gpio0d_e;
+ unsigned int gpio0a_p;
+ unsigned int gpio0b_p;
+ unsigned int gpio0c_p;
+ unsigned int gpio0d_p;
+ unsigned int gpio0al_iomux;
+ unsigned int gpio0bl_iomux;
+ unsigned int gpio0cl_iomux;
+ unsigned int gpio0dl_iomux;
+ unsigned int gpio0l_sr;
+ unsigned int gpio0h_sr;
+ unsigned int gpio0l_smt;
+ unsigned int gpio0h_smt;
+ unsigned int reserved1[(0x100 - 0x3c) / 4 - 1];
+ unsigned int soc_con[4];
+ unsigned int reserved2[(0x180 - 0x10c) / 4 - 1];
+ unsigned int pvtm_con[2];
+ unsigned int reserved3[2];
+ unsigned int pvtm_status[2];
+ unsigned int reserved4[(0x200 - 0x194) / 4 - 1];
+ unsigned int os_reg[12];
+ unsigned int reset_function_status;
+};
+
+check_member(px30_pmugrf, reset_function_status, 0x230);
+
+#endif
------------------------ include/configs/px30_common.h -------------------------
new file mode 100644
index 0000000000..d6c70601dd
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __CONFIG_PX30_COMMON_H
+#define __CONFIG_PX30_COMMON_H
+
+#include "rockchip-common.h"
+
+#define CONFIG_SYS_CBSIZE 1024
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_SYS_NS16550_MEM32
+
+#define CONFIG_ROCKCHIP_STIMER_BASE 0xff220020
+#define COUNTER_FREQUENCY 24000000
+
+/* FIXME: ff020000 is pmu_mem (10k), while ff0e0000 is regular int_mem */
+#define CONFIG_IRAM_BASE 0xff020000
+
+#define CONFIG_SYS_INIT_SP_ADDR 0x00400000
+#define CONFIG_SYS_LOAD_ADDR 0x00800800
+#define CONFIG_SPL_STACK 0x00400000
+#define CONFIG_SPL_MAX_SIZE 0x20000
+#define CONFIG_SPL_BSS_START_ADDR 0x4000000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x4000
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
+
+#define GICD_BASE 0xff131000
+#define GICC_BASE 0xff132000
+
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
+
+/* MMC/SD IP block */
+//#define CONFIG_BOUNCE_BUFFER
+
+#define CONFIG_SYS_SDRAM_BASE 0
+#define SDRAM_MAX_SIZE 0xff000000
+#define SDRAM_BANK_SIZE (2UL << 30)
+
+#ifndef CONFIG_SPL_BUILD
+
+#define ENV_MEM_LAYOUT_SETTINGS \
+ "scriptaddr=0x00500000\0" \
+ "pxefile_addr_r=0x00600000\0" \
+ "fdt_addr_r=0x08300000\0" \
+ "kernel_addr_r=0x00280000\0" \
+ "kernel_addr_c=0x03e80000\0" \
+ "ramdisk_addr_r=0x0a200000\0"
+
+#include <config_distro_bootcmd.h>
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ ENV_MEM_LAYOUT_SETTINGS \
+ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ "partitions=" PARTS_DEFAULT \
+ ROCKCHIP_DEVICE_SETTINGS \
+ BOOTENV
+
+#endif
+
+#endif
-------------------- include/dt-bindings/power/px30-power.h --------------------
new file mode 100644
index 0000000000..30917a99ad
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __DT_BINDINGS_POWER_PX30_POWER_H__
+#define __DT_BINDINGS_POWER_PX30_POWER_H__
+
+/* VD_CORE */
+#define PX30_PD_A35_0 0
+#define PX30_PD_A35_1 1
+#define PX30_PD_A35_2 2
+#define PX30_PD_A35_3 3
+#define PX30_PD_SCU 4
+
+/* VD_LOGIC */
+#define PX30_PD_USB 5
+#define PX30_PD_DDR 6
+#define PX30_PD_SDCARD 7
+#define PX30_PD_CRYPTO 8
+#define PX30_PD_GMAC 9
+#define PX30_PD_MMC_NAND 10
+#define PX30_PD_VPU 11
+#define PX30_PD_VO 12
+#define PX30_PD_VI 13
+#define PX30_PD_GPU 14
+
+/* VD_PMU */
+#define PX30_PD_PMU 15
+
+#endif
----------------- include/dt-bindings/soc/rockchip,boot-mode.h -----------------
new file mode 100644
index 0000000000..4b0914c098
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ROCKCHIP_BOOT_MODE_H
+#define __ROCKCHIP_BOOT_MODE_H
+
+/*high 24 bits is tag, low 8 bits is type*/
+#define REBOOT_FLAG 0x5242C300
+/* normal boot */
+#define BOOT_NORMAL (REBOOT_FLAG + 0)
+/* enter bootloader rockusb mode */
+#define BOOT_BL_DOWNLOAD (REBOOT_FLAG + 1)
+/* enter recovery */
+#define BOOT_RECOVERY (REBOOT_FLAG + 3)
+ /* enter fastboot mode */
+#define BOOT_FASTBOOT (REBOOT_FLAG + 9)
+
+#endif