ARM: dts: rockchip: Remove @0 from the veyron memory node
From: Heiko Stuebner <heiko@...> Date: Sun, 18 Nov 2018 20:03:02 +0100
Commit-Message
The Coreboot version on veyron ChromeOS devices seems to ignore memory@0 nodes when updating the available memory and instead inserts another memory node without the address. This leads to 4GB systems only ever be using 2GB as the memory@0 node takes precedence. So remove the @0 for veyron devices. Fixes: 0b639b815f15 ("ARM: dts: rockchip: Add missing unit name to memory nodes in rk3288 boards") Cc: stable@vger.kernel.org Reported-by: Heikki Lindholm <holin@...> Signed-off-by: Heiko Stuebner <heiko@...>
Patch-Comment
arch/arm/boot/dts/rk3288-veyron.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)
Statistics
- 5 lines added
- 1 lines removed
Changes
--------------------- arch/arm/boot/dts/rk3288-veyron.dtsi ---------------------
index 2075120cfc4d..d8bf939a3aff 100644
@@ -10,7 +10,11 @@
#include "rk3288.dtsi"
/ {
+ /*
+ * The default coreboot on veyron devices ignores memory@0 nodes
+ * and would instead create another memory node.
+ */
+ memory {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};