PatchTrack

From: Heiko Stuebner <heiko.stuebner@...> Date: Tue, 11 Jul 2023 14:04:18 +0200

This series provides cryptographic implementations using the vector crypto extensions. v13 of the vector patchset dropped the patches for in-kernel usage of vector instructions, I picked the ones from v12 over into this series for now. My basic goal was to not re-invent cryptographic code, so the heavy lifting is done by those perl-asm scripts used in openssl and the perl code used here-in stems from code that is targetted at openssl [0] and is unmodified from there to limit needed review effort. With a matching qemu (there are patches for vector-crypto flying around) the in-kernel crypto-selftests (also the extended ones) are very happy so far. changes in v4: - split off from scalar crypto patches but base on top of them - adapt to pending openssl code [0] using the now frozen vector crypto extensions - with all its changes [0] https://github.com/openssl/openssl/pull/20149 changes in v3: - rebase on top of 6.3-rc2 - rebase on top of vector-v14 patchset - add the missing Co-developed-by mentions to showcase the people that did the actual openSSL crypto code changes in v2: - rebased on 6.2 + zbb series, so don't include already applied changes anymore - refresh code picked from openssl as that side matures - more algorithms (SHA512, AES, SM3, SM4) Greentime Hu (2): riscv: Add support for kernel mode vector riscv: Add vector extension XOR implementation Heiko Stuebner (10): RISC-V: add helper function to read the vector VLEN RISC-V: add vector crypto extension detection RISC-V: crypto: update perl include with helpers for vector (crypto) instructions RISC-V: crypto: add Zvbb+Zvbc accelerated GCM GHASH implementation RISC-V: crypto: add Zvkg accelerated GCM GHASH implementation RISC-V: crypto: add a vector-crypto-accelerated SHA256 implementation RISC-V: crypto: add a vector-crypto-accelerated SHA512 implementation RISC-V: crypto: add Zvkned accelerated AES encryption implementation RISC-V: crypto: add Zvksed accelerated SM4 encryption implementation RISC-V: crypto: add Zvksh accelerated SM3 hash implementation arch/riscv/crypto/Kconfig | 68 ++- arch/riscv/crypto/Makefile | 44 +- arch/riscv/crypto/aes-riscv-glue.c | 168 ++++++ arch/riscv/crypto/aes-riscv64-zvkned.pl | 528 ++++++++++++++++++ arch/riscv/crypto/ghash-riscv64-glue.c | 245 ++++++++ arch/riscv/crypto/ghash-riscv64-zvbb-zvbc.pl | 378 +++++++++++++ arch/riscv/crypto/ghash-riscv64-zvkg.pl | 166 ++++++ arch/riscv/crypto/riscv.pm | 446 ++++++++++++++- arch/riscv/crypto/sha256-riscv64-glue.c | 115 ++++ .../crypto/sha256-riscv64-zvbb-zvknha.pl | 312 +++++++++++ arch/riscv/crypto/sha512-riscv64-glue.c | 106 ++++ .../crypto/sha512-riscv64-zvbb-zvknhb.pl | 375 +++++++++++++ arch/riscv/crypto/sm3-riscv64-glue.c | 112 ++++ arch/riscv/crypto/sm3-riscv64-zvksh.pl | 223 ++++++++ arch/riscv/crypto/sm4-riscv64-glue.c | 162 ++++++ arch/riscv/crypto/sm4-riscv64-zvksed.pl | 298 ++++++++++ arch/riscv/include/asm/hwcap.h | 9 + arch/riscv/include/asm/vector.h | 28 + arch/riscv/include/asm/xor.h | 82 +++ arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/cpu.c | 8 + arch/riscv/kernel/cpufeature.c | 50 ++ arch/riscv/kernel/kernel_mode_vector.c | 132 +++++ arch/riscv/lib/Makefile | 1 + arch/riscv/lib/xor.S | 81 +++ 25 files changed, 4127 insertions(+), 11 deletions(-) create mode 100644 arch/riscv/crypto/aes-riscv-glue.c create mode 100644 arch/riscv/crypto/aes-riscv64-zvkned.pl create mode 100644 arch/riscv/crypto/ghash-riscv64-zvbb-zvbc.pl create mode 100644 arch/riscv/crypto/ghash-riscv64-zvkg.pl create mode 100644 arch/riscv/crypto/sha256-riscv64-glue.c create mode 100644 arch/riscv/crypto/sha256-riscv64-zvbb-zvknha.pl create mode 100644 arch/riscv/crypto/sha512-riscv64-glue.c create mode 100644 arch/riscv/crypto/sha512-riscv64-zvbb-zvknhb.pl create mode 100644 arch/riscv/crypto/sm3-riscv64-glue.c create mode 100644 arch/riscv/crypto/sm3-riscv64-zvksh.pl create mode 100644 arch/riscv/crypto/sm4-riscv64-glue.c create mode 100644 arch/riscv/crypto/sm4-riscv64-zvksed.pl create mode 100644 arch/riscv/include/asm/xor.h create mode 100644 arch/riscv/kernel/kernel_mode_vector.c create mode 100644 arch/riscv/lib/xor.S -- 2.39.2

Patches in this set

• [0001] riscv: Add support for kernel mode vector (raw)
• [0002] riscv: Add vector extension XOR implementation (raw)
• [0003] RISC-V: add helper function to read the vector VLEN (raw)
• [0004] RISC-V: add vector crypto extension detection (raw)
• [0005] RISC-V: crypto: update perl include with helpers for (raw)
• [0006] RISC-V: crypto: add Zvbb+Zvbc accelerated GCM GHASH (raw)
• [0007] RISC-V: crypto: add Zvkg accelerated GCM GHASH (raw)
• [0008] RISC-V: crypto: add a vector-crypto-accelerated SHA256 (raw)
• [0009] RISC-V: crypto: add a vector-crypto-accelerated SHA512 (raw)
• [0010] RISC-V: crypto: add Zvkned accelerated AES encryption (raw)
• [0011] RISC-V: crypto: add Zvksed accelerated SM4 encryption (raw)
• [0012] RISC-V: crypto: add Zvksh accelerated SM3 hash (raw)

Statistics

• 12 individual patches
• 4131 lines added
• 15 lines removed