From 27c3cee41fe13359d962babc793dd40e18792491 Mon Sep 17 00:00:00 2001
From: Jianqun <jay.xu@rock-chips.com>
Date: Mon, 1 Sep 2014 23:56:28 +0200
Subject: [PATCH 02/11] clk: rockchip: fix rk3288 pll status register location

In RK3288, APLL lock status bit is in GRF_SOC_STATUS1,
but in RK3188, is GRFSOC_STATUS0.

Signed-off-by: Jianqun <jay.xu@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Heiko Stuebner <heiko@sntech.de>
---
 drivers/clk/rockchip/clk-rk3288.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index 038b1aa..4586578 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -20,7 +20,7 @@
 #include "clk.h"
 
 #define RK3288_GRF_SOC_CON(x)	(0x244 + x * 4)
-#define RK3288_GRF_SOC_STATUS	0x280
+#define RK3288_GRF_SOC_STATUS	0x284
 
 enum rk3288_plls {
 	apll, dpll, cpll, gpll, npll,
-- 
2.0.1