clk: rockchip: fix cpuclk mux bit of big cpu-cluster
From: Heiko Stuebner <heiko@...> Date: Tue, 19 Jan 2016 10:01:08 +0100
Commit-Message
Both clusters have their mux bit in bit 7 of their respective register. For whatever reason the big cluster currently lists bit 15 which is definitly wrong. Fixes: 3536c97a52db ("clk: rockchip: add rk3368 clock controller") Reported-by: Zhang Qing <zhangqing@...> Signed-off-by: Heiko Stuebner <heiko@...>
Patch-Comment
I plan to include them into my clk-fixes branch, so posted for reference and possible objections ;-) drivers/clk/rockchip/clk-rk3368.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Statistics
- 1 lines added
- 1 lines removed
Changes
---------------------- drivers/clk/rockchip/clk-rk3368.c -----------------------
index 21f3ea9..f6667b8 100644
@@ -165,7 +165,7 @@ static const struct rockchip_cpuclk_reg_data rk3368_cpuclkb_data = {
.core_reg = RK3368_CLKSEL_CON(0),
.div_core_shift = 0,
.div_core_mask = 0x1f,
+ .mux_core_shift = 7,
};
static const struct rockchip_cpuclk_reg_data rk3368_cpuclkl_data = {