drm/rockchip: dw-mipi-dsi: add support for
From: Heiko Stuebner <heiko@...> Date: Sun, 16 Dec 2018 12:01:44 +0100
Commit-Message
Add the compatible and grf values and allow the driver to also not select a specific crtc input on systems with only one vop. Signed-off-by: Heiko Stuebner <heiko@...>
Patch-Comment
.../display/rockchip/dw_mipi_dsi_rockchip.txt | 1 + .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 25 +++++++++++++++++-- 2 files changed, 24 insertions(+), 2 deletions(-)
Statistics
- 24 lines added
- 2 lines removed
Changes
- Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt --
index 6bb59ab39f2f..869fbc256d51 100644
@@ -5,6 +5,7 @@ Required properties:
- #address-cells: Should be <1>.
- #size-cells: Should be <0>.
- compatible: "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi".
+ "rockchip,rk3368-mipi-dsi", "snps,dw-mipi-dsi".
"rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi".
- reg: Represent the physical address range of the controller.
- interrupts: Represent the controller's interrupt to the CPU(s).
--------------- drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c ----------------
index 7ee359bcee62..041647bfce71 100644
@@ -142,6 +142,11 @@
#define RK3288_DSI0_LCDC_SEL BIT(6)
#define RK3288_DSI1_LCDC_SEL BIT(9)
+#define RK3368_GRF_SOC_CON7 0x41c
+#define RK3368_DSI_TURNDISABLE BIT(5)
+#define RK3368_DSI_FORCERXMODE BIT(6)
+#define RK3368_DSI_FORCETXSTOPMODE (0xf << 7)
+
#define RK3399_GRF_SOC_CON20 0x6250
#define RK3399_DSI0_LCDC_SEL BIT(0)
#define RK3399_DSI1_LCDC_SEL BIT(4)
@@ -192,7 +197,7 @@ enum {
struct rockchip_dw_dsi_chip_data {
u32 reg;
+ int lcdsel_grf_reg;
u32 lcdsel_big;
u32 lcdsel_lit;
@@ -566,7 +571,7 @@ static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_rockchip_phy_ops = {
static void dw_mipi_dsi_rockchip_config(struct dw_mipi_dsi_rockchip *dsi,
int mux)
{
+ if (dsi->cdata->lcdsel_grf_reg >= 0)
regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg,
mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big);
@@ -1008,6 +1013,19 @@ static const struct rockchip_dw_dsi_chip_data rk3288_chip_data[] = {
{ /* sentinel */ }
};
+static const struct rockchip_dw_dsi_chip_data rk3368_chip_data[] = {
+ {
+ .reg = 0xff960000,
+ .lcdsel_grf_reg = -1,
+ .lanecfg1_grf_reg = RK3368_GRF_SOC_CON7,
+ .lanecfg1 = HIWORD_UPDATE(0, RK3368_DSI_TURNDISABLE |
+ RK3368_DSI_FORCERXMODE |
+ RK3368_DSI_FORCETXSTOPMODE),
+ .max_data_lanes = 4,
+ },
+ { /* sentinel */ }
+};
+
static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = {
{
.reg = 0xff960000,
@@ -1058,6 +1076,9 @@ static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = {
{
.compatible = "rockchip,rk3288-mipi-dsi",
.data = &rk3288_chip_data,
+ }, {
+ .compatible = "rockchip,rk3368-mipi-dsi",
+ .data = &rk3368_chip_data,
}, {
.compatible = "rockchip,rk3399-mipi-dsi",
.data = &rk3399_chip_data,